Synopsys, Inc. (SNPS) - Deep Dive Research Report

Report Date: May 9, 2026 Analyst: Equity Research, Technology Coverage

Section 1: What the Company Does

Synopsys makes the software that makes chips possible. Without Synopsys, the engineers at Apple, NVIDIA, AMD, Qualcomm, Samsung, and every other semiconductor company designing chips today could not do their jobs. The company does not design chips itself. It sells the tools, automation software, and building-block intellectual property that chip designers use - the same way a builder uses AutoCAD but does not become an architect.

The core business, which the company has built over nearly four decades, is Electronic Design Automation - EDA. A modern chip like an Apple A-series processor or NVIDIA's Blackwell GPU contains tens of billions of transistors arranged in patterns so intricate that no human team could design them by hand. Synopsys provides the software environment in which chip engineers describe what they want a chip to do, translate that description into a physical layout of silicon gates, simulate whether it will work correctly at speed, verify that no errors exist, and hand off production-ready files to a foundry like TSMC or Samsung to manufacture. This process - from conceptual register-transfer-level description to the GDSII file that a foundry stamps onto silicon - runs almost entirely on Synopsys software.

The founding story matters for understanding the current business. On December 18, 1986, Aart de Geus, a Belgian-born engineer who had been working at General Electric, left with two colleagues - David Gregory and Bill Krieger - to found Optimal Solutions Inc. in Research Triangle Park, North Carolina. GE backed the spin-off with $400,000 for equity. De Geus had spent years at GE's Microelectronics Center trying to automate the tedious, error-prone manual process of translating chip behavior descriptions into manufacturable circuit netlists. In 1987, the company moved to Silicon Valley and was renamed Synopsys - a portmanteau of "synthesis" and "optimization." The flagship product, Design Compiler, automated logic synthesis: the translation of high-level hardware description language into an optimized gate-level circuit. This was genuinely novel. The company went public in February 1992, turning GE's $400,000 stake into $23 million. De Geus led the company as CEO from 1994 until he handed the reins to Sassine Ghazi in January 2024, remaining as Executive Chair.

The problem Synopsys solves keeps getting harder, which is why the company keeps growing. Moore's Law - the observation that transistor counts double roughly every two years - means each new chip generation packs more complexity into less space at lower power. A 2nm chip being designed today at TSMC has an order of magnitude more design rules, more interaction effects between adjacent components, and more modes of failure than a chip from a decade ago. The cost of a design mistake is catastrophic: a tape-out (sending a chip design to the foundry to make physical silicon) at advanced nodes costs tens of millions of dollars, and if the chip has a bug, the company must respin at equivalent cost and timeline. Synopsys's tools are the layer that catches those bugs before tape-out.

In January 2024, Synopsys announced its most consequential strategic move: the $35 billion acquisition of Ansys, the dominant provider of multiphysics engineering simulation software. Ansys lets engineers simulate how physical forces - heat, stress, electromagnetic fields, fluid dynamics - affect a product in the real world. The deal closed July 17, 2025, transforming Synopsys from an EDA company (chip design software) into what management now calls "the leader in engineering solutions from silicon to systems." The logic is that the increasing complexity of modern AI hardware - chips running hot in data centers, sensors in autonomous vehicles exposed to vibration and extreme temperature, automotive electronics that must survive 15-year lifecycles - requires simultaneous optimization of electronic design and physical behavior. Synopsys can now offer both in an integrated platform, which neither Cadence nor Siemens EDA can match.

To walk through what the company actually does for a customer: a hyperscale cloud company like Google decides to design a custom AI inference chip for its data centers. The design team opens Synopsys Fusion Compiler and describes the chip's logic in RTL (register-transfer level) code. DSO.ai, Synopsys's reinforcement-learning tool, explores tens of thousands of possible physical layouts to optimize power, performance, and chip area - a process that used to take months of expert human time and now takes days. VCS, Synopsys's simulation tool, runs billions of test vectors to verify the logic works correctly under every possible input. ZeBu emulation hardware creates a physical FPGA-based model of the chip so software engineers can develop operating system code and applications on real hardware months before silicon arrives. PrimeTime performs final timing sign-off. IC Validator runs physical design rule checks. When the GDSII file goes to TSMC, Synopsys manufacturing tools model the lithography process to ensure patterns print correctly at the desired linewidth. After the Ansys acquisition, that same design team can now model heat dissipation inside the chip package, structural stress on PCB solder joints, and electromagnetic interference - all within an integrated Synopsys workflow. Throughout, the team uses DesignWare IP - pre-verified PCIe, HBM, and CXL interface blocks from Synopsys that they drop directly into their design rather than building from scratch.

The total addressable market Synopsys competes in expanded from approximately $19 billion (EDA alone) to approximately $31 billion (EDA plus simulation and analysis) following the Ansys acquisition.

Section 2: Business Segments

Synopsys reports two business segments: Design Automation and Design IP. Post-Ansys, the Design Automation segment absorbed the entire Ansys simulation business, making it the dominant segment by revenue.

2.1 Design Automation (~75% of Revenue)

Design Automation encompasses everything Synopsys provides to help an engineer take a chip from conceptual description to manufacturable design. It contains three distinct sub-businesses that travel under the same reporting umbrella: EDA software, Hardware-Assisted Verification hardware, and - post-July 2025 - the Ansys simulation and analysis portfolio.

EDA Software is where the company was built and where it still generates the largest share of recurring revenue. The software suite covers the complete chip design flow. On the digital design side, Fusion Compiler is the flagship RTL-to-GDSII tool - it handles synthesis (translating logic description to gates), place-and-route (arranging gates on silicon and connecting them with wires), and signoff (verifying the design meets timing, power, and area targets). Design Compiler is the foundational synthesis engine that many customers have used for two decades. Custom Compiler handles analog and mixed-signal circuit design, where transistors are drawn and simulated individually rather than synthesized automatically. PrimeTime is the industry's standard static timing analysis tool - virtually every chip tapeout runs through PrimeTime for timing signoff. RedHawk-SC handles power integrity analysis, critical for chips with billions of switching transistors creating local voltage fluctuations that can cause failures. IC Validator performs physical verification - checking that every feature of the layout satisfies the foundry's thousands of design rules. Formality provides formal equivalence checking, mathematically proving that the synthesized netlist is logically identical to the original RTL description. For multi-die designs and 3D-IC packaging (where multiple chiplets are stacked or placed on an interposer), Synopsys offers 3DIC Compiler, which is rapidly becoming a mission-critical tool as AI chip designers increasingly turn to chiplet architectures to manage die size and yield.

The EDA software business runs almost entirely on subscription/time-based licenses. Customers sign multi-year contracts typically ranging from three to five years that grant access to a bundle of tools. Because the tools become deeply embedded in customer workflows - engineers build scripts, automation, and institutional knowledge around specific Synopsys tools over years or decades - renewal rates are extremely high. Management has characterized this as an "80%+ recurring revenue" model. The EDA software business does not have major hardware capital expenditure requirements: it is fundamentally a software business with very high gross margins.

Hardware-Assisted Verification (HAV) is the segment's fastest-growing sub-business and a significant competitive differentiator. As chips grow larger and more complex, software simulation alone becomes prohibitively slow - verifying a billion-gate chip by running it in software simulation would take years of computer time. HAV solves this by building a hardware replica of the chip in progress using FPGAs (field-programmable gate arrays), allowing the design to be validated at speeds millions of times faster than software simulation.

Synopsys's HAV product families are ZeBu and HAPS. ZeBu is an emulation system - it creates a reconfigurable hardware model of the chip that design teams use to run comprehensive functional verification, catch subtle hardware bugs, and run real software (operating systems, drivers, applications) against the not-yet-manufactured chip. The current generation, ZeBu-200, was released in early 2025 and offers up to 2x higher runtime performance compared to its predecessor, with scalability beyond 60 billion gates to handle the enormous complexity of modern AI chip SoC designs. HAPS (High-speed ASIC Prototyping System) is Synopsys's prototyping platform - similar in principle but oriented toward enabling software teams to develop code and validate system integration at higher speeds than emulation, and also used for interface protocol compliance certification. HAPS-200 delivers up to 2x performance and 4x debug bandwidth versus HAPS-100. Both platforms share the EP-Ready Hardware platform built on AMD's latest FPGA innovations.

HAV revenues are hardware revenues, meaning they are non-recurring and can be lumpy quarter-to-quarter. However, the installed base creates a long-tail of service and upgrade revenue. In Q4 FY2025, HAV achieved record results with 12 competitive wins in the quarter. Management has consistently highlighted this business as a key growth driver and competitive moat against Cadence, which offers the Palladium emulation system as its equivalent.

Ansys Simulation and Analysis is the newest and potentially most transformative part of the Design Automation segment. Ansys was, prior to the acquisition, the world's leading provider of engineering simulation software. The Ansys portfolio spans: structural analysis (how materials deform and fail under load, used in everything from aerospace fuselages to semiconductor package substrates); fluid dynamics (how liquids and gases flow, used in chip cooling, aerospace, and automotive aerodynamics); electromagnetic simulation (antenna design, signal integrity, EMI/EMC compliance); optics and photonics; and systems simulation (connecting different physics domains to model entire products). Ansys's customer base before the acquisition was broader than semiconductor companies - it includes aerospace and defense contractors, automotive OEMs, industrial manufacturers, and consumer electronics firms. GE, Boeing, Airbus, Ford, and hundreds of other industrial companies use Ansys tools to simulate product behavior long before building physical prototypes.

Synopsys acquired Ansys specifically to close the "silicon-to-systems" gap. A chip engineer at NVIDIA can design the Blackwell GPU using Synopsys EDA tools, but the thermal behavior of that chip running at full load inside a data center rack - the heat dissipation through the package, the airflow patterns required, the mechanical stress on package solder joints over thousands of thermal cycles - that has traditionally been simulated separately using Ansys or similar tools, by different teams, using different software. Synopsys's vision is to integrate these workflows so a chip designer can simultaneously optimize electronic performance and physical behavior in one connected environment.

The Ansys acquisition is still in integration. First joint product capabilities are expected H1 2026. Revenue synergy targets are $400 million by year four post-close (approximately FY2029). In FY2025 post-close (partial year), Ansys contributed $756.6 million in revenue to Design Automation. For FY2026, Ansys is expected to contribute approximately $2.9 billion, with management guiding for double-digit organic growth in that business.

Note a nuance in revenue model: Synopsys is deliberately transitioning some Ansys product lines (particularly semiconductor-focused simulation tools) from upfront/perpetual license models to subscription-ratable recognition models. This creates near-term revenue headwinds as revenue is deferred and recognized over subscription periods, but improves long-term revenue predictability.

Competitive position within Design Automation: Synopsys holds approximately 38% of the global EDA market, roughly tied with Cadence Design Systems (approximately 36%). Siemens EDA (formerly Mentor Graphics) is third at approximately 13%. Against Cadence, Synopsys competes head-to-head on digital design (Synopsys Fusion Compiler vs. Cadence Innovus), simulation (Synopsys VCS vs. Cadence Xcelium), emulation (ZeBu vs. Palladium), and signoff (PrimeTime vs. Tempus). In hardware verification, Synopsys has been particularly aggressive and winning - 12 competitive HAV wins in Q4 FY2025 alone is significant given the installed-base nature of this market. On the simulation and analysis side, Ansys largely leaves Synopsys without a peer combination: Cadence has no comparable multiphysics simulation portfolio, and Siemens EDA's parent (Siemens AG) does own Siemens Digital Industries Software which has some simulation capabilities, but the integration with EDA is not as deep.

Strategic priority: This is the group's growth engine, margin driver, and the segment where the Ansys transformation is playing out. Management targets FY2026 non-GAAP operating margin of 40.5% at the group level, up 320 basis points year-over-year.

2.2 Design IP (~25% of Revenue)

Synopsys is the world's second-largest semiconductor IP provider, behind only ARM Holdings. The segment sells pre-designed, pre-verified building blocks - called intellectual property (IP) blocks or "silicon IP" - that chip designers incorporate directly into their designs rather than building from scratch.

Every modern chip contains dozens of standardized interface circuits that connect it to external components: a memory controller that talks to DRAM, a USB controller that connects to peripherals, a PCIe controller that connects to the system motherboard, an Ethernet MAC that connects to networks. Building these correctly at an advanced process node like 5nm or 3nm requires deep expertise in the specific protocol, high-speed analog circuit design, and foundry-specific optimization. Most chip design teams - even at sophisticated companies like Apple or Qualcomm - do not want to spend engineers and years building a USB 4.0 controller from scratch when they can license Synopsys's pre-validated, foundry-certified block and drop it in.

The DesignWare IP portfolio is organized into four main families:

Interface IP is the segment's largest and most strategically important family. It includes controllers and PHYs (physical layer circuits) for every major connectivity standard: PCIe (the dominant chip-to-board interconnect, now at Gen 6), CXL (the emerging high-bandwidth coherent interconnect for AI accelerator pools), DDR/LPDDR (memory interface, now at DDR5 and LPDDR5X), HBM (High Bandwidth Memory interface, critical for AI training chips where NVIDIA uses HBM2e/HBM3), USB (all versions including USB4), Ethernet (from 10GbE to 400GbE and beyond), MIPI (the standard for smartphone display and camera interfaces), DisplayPort, and HDMI. The critical point about interface IP is that it must be certified by foundries like TSMC and Samsung to work correctly at their specific process nodes. Synopsys invests continuously in maintaining this certification across every new process node, which creates a significant barrier for competitors - it takes years to build a certified IP portfolio across all major foundries and process nodes, and customers will not risk tape-out on uncertified IP.

Foundation IP consists of logic libraries (the fundamental building blocks - flip-flops, logic gates, buffers - that synthesis tools use to implement a chip's logic in a specific foundry's process), embedded memories (SRAM compilers that generate memory arrays optimized for a specific process node's performance-power-area tradeoffs), I/O libraries, and non-volatile memory. Foundation IP is largely process-specific - a library certified for TSMC N3 cannot be used for Samsung 4nm. Synopsys maintains certified libraries across dozens of process nodes at multiple foundries, which has taken decades to accumulate.

Security IP provides hardware root-of-trust solutions, cryptographic accelerators (AES, SHA, RSA, ECC), physical unclonable functions (PUFs), and random number generators. Security IP is increasingly mandatory as governments and enterprises demand hardware-level security in chips used in automotive, IoT, and data center applications.

Processor IP historically included Synopsys's ARC embedded processor family - soft cores used in hundreds of millions of devices from Bluetooth chips to automotive controllers. In Q1 FY2026, Synopsys announced the divestiture of its ARC processor IP solutions to GlobalFoundries. The strategic logic: the ARC business was a lower-growth, commoditized market competing against ARM, RISC-V open-source alternatives, and specialized proprietary processors. Synopsys is redirecting those resources toward interface IP, where growth driven by AI connectivity standards (CXL, HBM, PCIe Gen 6) is structurally stronger and margins are higher.

Why Design IP exists as a separate segment: The economics are different from EDA software. IP revenues include a mix of one-time license fees (when the IP is licensed for use in a specific design), royalties (ongoing payments per chip shipped, typically a fraction of a cent to a few cents per chip manufactured), and maintenance/support fees. The royalty stream is lower-margin than EDA software but valuable as it reflects the real-world adoption of IP into shipping products. However, the segment also includes custom IP engagements - where Synopsys builds bespoke IP to a customer's specification - which are human-capital-intensive engineering services with lower margin and delivery risk.

Design IP in FY2025 and FY2026: This segment has been the problem child. In Q3 FY2025, Design IP revenue declined 8% year-over-year, dragged down by three simultaneous headwinds: China export restrictions disrupting design starts (China was a heavy consumer of interface IP for domestic chip design), a major foundry customer facing its own market challenges delaying designs (reducing royalty-bearing tape-outs), and management's acknowledgment of "certain roadmap and resource decisions that did not yield intended results" - meaning Synopsys invested in IP products that failed to gain sufficient traction with customers.

In Q4 FY2025, full-year Design IP revenue was $1.75 billion, down 8% for FY2025. For FY2026, management guided for "muted growth" with a "transitional year" as the business reorients toward higher-growth interface IP protocols and away from the divested ARC processor business. The long-term target of mid-teens growth for Design IP was maintained.

Competitive position within Design IP: Against ARM's royalty-bearing processor IP, Synopsys does not compete directly (ARM is the dominant embedded processor IP provider). For interface IP, Synopsys competes primarily with Cadence (which has its own DesignWare-equivalent IP portfolio) and a collection of smaller pure-play IP vendors like Rambus (memory interface IP), Arteris IP (network-on-chip interconnect), and CEVA (wireless and audio IP). Synopsys's breadth - covering every major interface protocol across every major foundry and process node - is its differentiation. Customers prefer a single IP vendor for integration and support reasons; mixing IP from different vendors creates interoperability complexity that can delay tapeouts.

Summary comparison:

Section 3: Products and Business Detail

The EDA Software Suite

The core EDA product family at Synopsys addresses every stage of the chip design flow. Understanding the flow is essential to understanding the product portfolio.

Synthesis and Implementation: Design Compiler was the original product that made Synopsys - it translates RTL (register-transfer level) code written in Verilog or VHDL into a gate-level netlist, the first step in converting a behavioral description of a chip into something that can be physically manufactured. Fusion Compiler is the modern successor, integrating synthesis with physical implementation (place-and-route) in a unified environment that allows co-optimization - making synthesis decisions that account for physical layout constraints and vice versa. This integration reduces design iterations and improves PPA (power, performance, area) versus doing synthesis and place-and-route separately. For custom and analog circuits - the radio front-end in a smartphone, the high-speed I/O in a SerDes interface, the bandgap reference in a power management chip - Custom Compiler provides a schematic-driven design and simulation environment. 3DIC Compiler addresses the rapidly growing market for multi-die designs, where multiple separately manufactured chiplets are assembled on a common interposer or connected with hybrid bonding in 3D stacked configurations.

Verification: Verification is arguably the most labor-intensive and tool-intensive phase of chip design - estimates vary but many chip designers spend 60-70% of design effort on verification. VCS (Verilog Compiled Simulator) is Synopsys's logic simulation tool, the industry standard for running functional verification testbenches. SpyGlass and VC SpyGlass address RTL linting and static analysis - catching coding errors, reset issues, and clock-domain crossing problems before simulation. VC Formal provides formal verification capabilities - mathematically proving properties about a design rather than testing them through simulation.

Signoff: After implementation, a chip must be "signed off" - verified against a comprehensive set of physical and timing rules before tape-out. PrimeTime is the definitive industry standard for static timing analysis, used in virtually every production chip tape-out globally. IC Validator performs physical design rule checking (DRC) and layout versus schematic (LVS) - verifying that the physical layout matches the intended circuit and satisfies the foundry's thousands of manufacturing rules. RedHawk-SC analyzes power integrity across the chip, identifying voltage drops and electromigration risks. Formality provides formal equivalence checking to ensure the implemented netlist is functionally identical to the RTL.

Manufacturing: Synopsys provides a set of tools used by semiconductor manufacturers (foundries and IDMs) as well as chip designers for manufacturing preparation. Proteus is a computational lithography tool used for optical proximity correction (OPC) - the process of modifying mask shapes to compensate for optical effects in photolithography so that the printed features match the intended design. TCAD (Technology Computer-Aided Design) tools model semiconductor device physics - used by foundry process engineers to simulate and optimize transistor structures. Sentaurus Device and related tools allow engineers to model dopant profiles, carrier transport, and device characteristics at the quantum mechanical level.

AI Integration - Synopsys.ai: Since the early 2020 launch of DSO.ai, Synopsys has systematically embedded AI into its tool suite. DSO.ai (Design Space Optimization AI) uses reinforcement learning to explore enormous design spaces for optimal PPA tradeoffs in synthesis and place-and-route - a task that previously required teams of expert engineers manually tweaking settings across many design iterations. VSO.ai (Verification Space Optimization AI) applies AI to the verification problem - identifying which test scenarios to run to maximize coverage closure speed. Customers using these tools have reported 10x improvements in design turnaround time and 30%+ increases in verification productivity. As of Q4 FY2025, nearly 5,000 active users were working with Synopsys.ai. Management is actively developing "agentic AI" capabilities - AI systems that can orchestrate multi-step design tasks autonomously - with monetization expected in FY2027.

Hardware-Assisted Verification Products

ZeBu and HAPS are purpose-built physical systems, not software tools. A ZeBu system is a rack-mounted array of high-density FPGAs - often requiring significant data center floor space for large designs - that is programmed to replicate the logical behavior of the chip being designed. When an engineer "compiles" their chip design onto a ZeBu system, they can run real device drivers, operating system kernels, application software, and complex test sequences against the design at speeds 1,000x to 10,000x faster than pure software simulation. For an AI chip with a custom software stack - the kind Google or Amazon designs for their data centers - ZeBu is essential: software teams need to develop and debug their inference engines and training frameworks against the real hardware behavior before silicon arrives.

ZeBu Server 5 can scale beyond 60 billion gates, making it the largest-capacity emulation system available, required for the most complex AI SoC designs. ZeBu-200, announced in February 2025, is the next-generation scalable platform optimized for emerging multi-die and 3D-IC designs. HAPS-200 similarly advances the prototyping tier, offering 2x performance and 4x debug bandwidth over its predecessor.

In February 2026, Synopsys introduced what it called "Software-Defined Hardware-Assisted Verification" - a new architecture allowing customers to configure the same physical HAV hardware flexibly between emulation and prototyping modes, reducing the capital cost of maintaining separate emulation and prototyping infrastructure.

Ansys Simulation Portfolio

The Ansys suite, now part of Design Automation, covers five simulation physics domains:

Structural mechanics: Ansys Mechanical is the flagship tool, used by engineers worldwide to simulate how structures deform, vibrate, and fail under mechanical load, thermal stress, and fatigue. A semiconductor package engineer uses it to model how solder joints survive thousands of thermal cycles. An aerospace engineer uses it to certify that an aircraft fuselage panel meets fatigue life requirements.

Fluid dynamics: Ansys Fluent and CFX are computational fluid dynamics (CFD) tools, used for airflow modeling in chip cooling, aerodynamic analysis in vehicle design, and turbulence modeling in industrial equipment. Ansys ICEPAK specifically targets electronics thermal management - cooling analysis for PCBs, heat sinks, and system enclosures.

Electromagnetics: Ansys HFSS (High-Frequency Structure Simulator) is the dominant tool for high-frequency electromagnetic design - antenna simulation, signal integrity analysis, radar cross-section modeling. Ansys SIwave and Ansys Q3D address board-level signal and power integrity. These products directly overlap with and extend Synopsys's Raptor X tool that was used for chip-level electromagnetic analysis.

Systems simulation: Ansys Twin Builder and related tools create "digital twins" - simulation models of complete products that can mirror the behavior of physical products in real-time, used for predictive maintenance and design optimization.

Optics and photonics: Ansys Zemax (formerly OpticStudio) is the standard tool for optical system design - camera lenses, lidar sensors, laser systems. Given the growth of lidar in automotive ADAS and the emergence of co-packaged optics in data center networking, this is a strategically valuable asset.

Geographies

Synopsys sells globally, with design teams in North America, Europe, Asia-Pacific, Israel, and India. The United States generates the largest share of revenue by customer billing location, followed by Asia-Pacific (excluding China) and Europe. China has historically been an important market - contributing approximately 16% of FY2024 revenue - driven by the hundreds of domestic chip design companies (fabless companies) that proliferated in China during the 2010s and early 2020s. The impact of U.S. export restrictions (discussed in detail in the Risks section) reduced China's contribution to approximately 10% of revenue as of the FY2025 exit rate.

Key Milestones

• 1987: Design Compiler launched - first commercial logic synthesis tool
• 1992: IPO on NASDAQ
• 2002: Acquisition of Avant! (layout tools), beginning of full-flow coverage
• 2012: Acquisition of Magma Design Automation (further physical design tools), significantly strengthening the full-flow competitive position
• 2020: Launch of DSO.ai - first autonomous AI chip design tool
• 2022: Launch of 3DIC Compiler - targeting the chiplet design market
• 2024 (September): Divestiture of Software Integrity Group (Black Duck) to Clearlake and Francisco Partners for up to $2.1 billion
• 2025 (July): Completion of Ansys acquisition for approximately $35 billion - defining strategic transformation
• 2025 (December): NVIDIA $2 billion equity investment and strategic partnership announcement
• 2026 (Q1): Divestiture of ARC Processor IP to GlobalFoundries; $250M accelerated share repurchase initiated

Section 4: Customers

Who Buys

Synopsys sells to essentially every company that designs custom silicon - a list that has expanded dramatically over the past decade. The traditional customer base was semiconductor companies: chip designers like Qualcomm, MediaTek, Broadcom, Marvell, and AMD that design chips and outsource manufacturing to foundries. Foundries themselves - TSMC, Samsung Foundry, GlobalFoundries, UMC - are customers that use Synopsys manufacturing tools and maintain certified design flows.

The more recent growth driver is the hyperscaler segment: Microsoft, Google (Alphabet), Amazon (AWS), Meta, and others that have built semiconductor design teams to create custom AI accelerators, networking chips, and general-purpose compute processors. Apple has been doing this for years with its A-series and M-series chips and is one of the most sophisticated chip design organizations in the world. Each of these hyperscaler chip projects runs on Synopsys tools. The importance of this segment is that these companies have enormous design budgets, typically use leading-edge process nodes (2nm, 3nm), and require the most sophisticated design and verification tools available.

For the Ansys portion of the business, the customer universe is broader and includes industrial manufacturers, automotive OEMs and Tier 1 suppliers, aerospace and defense contractors, consumer electronics companies, and energy companies. These customers use simulation tools for mechanical, thermal, electromagnetic, and fluid analysis, and many of them are entirely separate from the semiconductor industry.

The Buying Decision

Within a semiconductor company, the buying decision for EDA tools sits with the engineering organization - typically the VP of Design Engineering or Chief Technology Officer, with input from the design methodology team (a group of experts who establish and maintain the flows and tool configurations used by all chip designers). EDA procurement is rarely a competitive tender for individual tools. Instead, companies negotiate enterprise agreements - multi-year licenses that give engineering teams access to a defined bundle of tools. Contract cycles tend to be three to five years. The key criteria: does this tool work correctly at the process node we are designing for? Does it have foundry certification? Does it deliver competitive PPA? Is it supported by a responsive applications engineering team? For hardware emulation and prototyping, decisions also factor in capacity, scalability, and integration with the simulation and debug tools already in use.

For Ansys customers in non-semiconductor industries, decisions sit with engineering leadership and procurement. Simulation software in aerospace and automotive is often mandated at the enterprise level - a Boeing or Airbus certifies specific simulation tools for specific calculation types as part of their engineering process qualification, and switching away from a certified tool requires re-qualifying the process. This creates powerful lock-in.

Switching Costs

Synopsys's switching costs are among the highest in enterprise software, for several compounding reasons.

First, tool certifications: foundries certify specific tool versions against their process design kits (PDKs). A design at TSMC N3 that uses Synopsys Fusion Compiler is validated against a specific version of the PDK and tool. Switching to Cadence Innovus partway through a design project would require re-qualifying the entire flow - testing with the foundry to confirm timing, DRC, and LVS results match with the new tool. Chip projects run on timelines of 12-24 months from concept to tape-out. No design team is willing to absorb the schedule risk of switching tools mid-project.

Second, accumulated institutional knowledge: chip design teams build scripts, run-decks (collections of tool commands for specific tasks), and automation that are specific to their tool set. A design team at NVIDIA that has been using Synopsys VCS for functional simulation for fifteen years has millions of lines of testbench code, verification IP, and automation scripted around VCS. Migrating to Cadence Xcelium would require porting all of this infrastructure.

Third, the cost of being wrong: the cost of discovering a bug after tape-out at a leading-edge node is catastrophic. EDA customers do not switch tools to save money on software licenses; they use tools they trust, with applications engineers they know, running on flows they have validated. The economic calculus strongly favors incumbency.

Fourth, multi-year enterprise agreements: most EDA customers sign three-to-five-year enterprise agreements, locking in at a negotiated price. Terminating early would be costly. This means Synopsys's relationship with a customer is structurally stable over most of a chip design cycle.

The result is customer lifetime relationships that span decades. The Arvy research cited by industry analysts notes customer retention rates implying "customer lifetimes easily spanning 20 years or more."

Concentration and Contract Structure

Synopsys does not publicly disclose customer concentration at the individual account level, but the company explicitly notes that no single customer accounts for more than 10% of revenue. Across more than 2,000 customers, the revenue is distributed enough that no single customer departure would be a company-defining event. That said, the hyperscaler chip design teams (Apple, NVIDIA, Google, Microsoft, Amazon) represent very large contracts individually and their loss would be meaningful. These customers are also, however, among the most demanding and sophisticated - their design teams stay current on the latest tools and nodes, and their use of Synopsys tools is deeply validated.

The revenue model is predominantly subscription-based with ratable revenue recognition. The backlog - contracts signed but not yet revenue-recognized - was $11.4 billion exiting FY2025 and $11.3 billion exiting Q1 FY2026. This backlog provides exceptional forward revenue visibility; management can see approximately 15 months of revenue at any given time, which is unusual even among enterprise software companies.

Section 5: Competitive Landscape

EDA - The Duopoly

The EDA market is structurally unlike most software markets: it is a stable duopoly between Synopsys and Cadence Design Systems that has persisted for decades. Together they hold approximately 74% of global EDA revenue. Siemens EDA (the former Mentor Graphics, acquired by Siemens AG in 2017) is the third player at approximately 13% global share. No other company has more than a few percent.

Why has the duopoly persisted? The barriers to entry in EDA are among the highest in enterprise software:

• Foundry certification: Every tool must be certified by TSMC, Samsung, GlobalFoundries, and Intel Foundry at every new process node. Maintaining certifications across N5, N3, N2, and A14 simultaneously requires deep, sustained investment in foundry relationships and tool validation. A new entrant would start with no certifications and could not sell tools for production tape-outs until certifications were earned - a process taking years.

• Accumulated algorithmic complexity: The algorithms inside EDA tools - synthesis optimization, routing algorithms, timing analysis, physical verification - have been developed and refined over decades by teams of PhDs. The PnR algorithms in Fusion Compiler reflect 30+ years of refinement by experts who understand every corner case in VLSI physical design. This is not knowledge that can be hired or purchased quickly.

• Customer switching costs: As described above, customers do not switch EDA tools during design cycles. This means the install base is essentially captive across multi-year windows, and new entrants can only win new design starts at margin - and even then, they must demonstrate foundry-certified, production-validated tools.

• Applications engineering force: Synopsys employs thousands of applications engineers who work directly with customer design teams to configure tools, write methodology documentation, and debug tool issues. This human infrastructure is as much a moat as the software itself - it enables the company to support complex customers at advanced nodes in ways that a smaller rival could not.

Synopsys vs. Cadence: On digital EDA (synthesis, PnR, simulation), the companies are roughly matched, and large chip design companies often use both - some workflows run on Synopsys, others on Cadence, and some customers deliberately dual-source to maintain negotiating leverage and avoid complete dependence. The competitive battle is intense but relatively stable. Neither company has dramatically taken share from the other in EDA software over the past decade.

On hardware-assisted verification, Synopsys has had the edge in recent years. ZeBu has been winning competitive contests against Cadence's Palladium platform, as evidenced by the 12 competitive wins in Q4 FY2025 alone. Hardware emulation systems are large capital purchases for chip design labs, and winning against an incumbent Palladium installation is notable.

On the simulation and analysis side, post-Ansys, Synopsys has no peer combination in the semiconductor market. Cadence has partial simulation capabilities - it acquired Numericraft and has integrated some electromagnetic simulation - but lacks the breadth and industry positioning of the Ansys portfolio.

Siemens EDA: Siemens acquired Mentor Graphics in 2017 for $4.5 billion, gaining a respected but smaller EDA portfolio. Siemens EDA has particular strength in the automotive domain (its Calibre physical verification tools are widely used) and in IC packaging design. In PCB design (a separate but adjacent market), Siemens EDA's Xpedition tool is a leading product. But in the core digital IC design flow (synthesis, PnR, simulation) that drives most EDA spending, Siemens is a distant third. Importantly, Siemens AG's parent-company connection gives Siemens EDA access to the automotive and industrial engineering community - the same market Ansys targets. This creates the clearest overlap: the merged Synopsys-Ansys entity and Siemens (EDA + Siemens Digital Industries simulation software) are likely to compete more directly in automotive and industrial simulation-heavy markets.

Simulation - Expanding Competition

In multiphysics simulation, Ansys (now Synopsys) has historically been the leading player. Competitors in specific domains include:

• Dassault Systemes (SIMULIA, ABAQUS): Strong in structural mechanics, widely used in aerospace and automotive. Dassault's Catia ecosystem gives it deep integration with mechanical CAD, which Ansys struggles to fully replicate.

• Hexagon (MSC Software): MSC Nastran is the legacy structural analysis standard in aerospace, mandated in many aerospace contracts. Hexagon also owns Adams (multibody dynamics) and Digimat (material modeling).

• Altair Engineering: Offers HyperWorks simulation suite with similar breadth to Ansys, typically more competitive on price. Strong in manufacturing (crash simulation, forming analysis).

• COMSOL: A specialized multiphysics tool with a strong academic following, used in electrochemistry, acoustics, and complex coupled-physics problems where Ansys tools are less flexible.

None of these competitors offers the integration with semiconductor chip design that Synopsys can build with the combined portfolio. The differentiator in the combined company is the connection from chip-level EDA through package-level electromagnetic and thermal simulation (where Ansys Mechanical and HFSS are strong) to system-level validation - a vertical integration that does not exist elsewhere.

China: Domestic EDA Competition

One area of genuine competitive concern is China. U.S. export restrictions on EDA tools to Chinese chip designers (discussed in detail in Risks) have created an opportunity for domestic Chinese EDA developers. Companies like EDA2 (a state-backed EDA consortium), Empyrean Technology (now publicly listed), and Primarius Technologies are developing local EDA tools, supported by government subsidies and demand from chip designers who cannot legally use U.S. software. These Chinese alternatives currently cover basic to intermediate design tasks - they are not competitive at advanced nodes (below 7nm). But the Chinese government's determination to build a domestic semiconductor design ecosystem means this investment will continue, and over time the capability gap will narrow. For Synopsys, the China competitive threat is not a near-term existential concern but is a structural headwind to long-term China market recovery.

Section 6: Industry

What Drives Demand for EDA and Simulation

EDA demand is primarily driven by chip design activity - the number of new chip design starts, their complexity (which determines how much tool usage per design), and the process nodes at which they are designed (advanced nodes require more sophisticated and expensive tools). Chip design activity is in turn driven by end-market demand for electronic products - smartphones, servers, networking equipment, automotive electronics, industrial controls - and by the intensity of competition among chipmakers, which drives investment in custom silicon.

The structural trends are strongly favorable:

AI silicon spending: The most important near-term demand driver is the insatiable demand for custom AI accelerators, networking chips, and memory controllers required for AI training and inference. NVIDIA, Google, Amazon, Microsoft, Meta, and dozens of startups are spending aggressively on chip design teams. AI chips push EDA demand in two ways: they require the most advanced process nodes (where tools are most expensive) and they are among the most complex chips ever designed, driving up hours of tool usage per design.

Hyperscaler custom silicon: Beyond AI accelerators, hyperscalers are designing custom CPUs (Amazon Graviton, Microsoft Maia, Google Axion), custom networking ASICs, and custom storage controllers. This represents a structural increase in the number of large, complex chip design projects running simultaneously.

3D-IC and chiplet architectures: As monolithic die sizes approach practical limits (yield and reticle size constraints), the industry is moving toward chiplet-based designs where multiple dies are integrated in a single package. This increases design complexity - managing die-to-die interfaces, thermal balance across chiplets, and package-level signal integrity - all requiring additional tool usage and new categories of tools (like 3DIC Compiler).

Automotive electrification: Software-defined vehicles require sophisticated silicon for ADAS, V2X communication, infotainment, and battery management. Automotive chip designs must meet much higher reliability and safety standards (ISO 26262 functional safety certification) than consumer chips, which increases verification intensity and tool usage.

Industry Size and Growth

The EDA software market (pre-Ansys combination) is estimated at approximately $16-19 billion in addressable spend for FY2025-2026, growing at a compound rate of approximately 8-10% annually. The Ansys acquisition expanded the combined addressable market to approximately $31 billion, including $12 billion in simulation and analysis.

The EDA market has historically been one of the most recession-resistant areas in technology: chip design activity continued through the 2020 pandemic with minimal disruption and has been elevated since by AI demand. The cyclicality of EDA is much lower than the semiconductor manufacturing cycle: chip design projects run 18-24 months and cannot be easily paused, so tool usage remains relatively stable even when chip inventories pile up at the end of a demand cycle.

Regulatory Environment

The dominant regulatory force affecting Synopsys is U.S. export controls on semiconductor technology. The Bureau of Industry and Security (BIS) regulates the export of EDA software and semiconductor IP under the Export Administration Regulations (EAR). In May 2025, BIS sent Synopsys a letter imposing restrictions on sales to Chinese entities, forcing Synopsys to halt new orders and block fulfillment in China within days of its Q2 FY2025 earnings call. These restrictions were rescinded on July 2, 2025, following a broader U.S.-China trade truce, but not before causing Synopsys to withdraw its full-year guidance in an unprecedented move. The episode illustrates how directly U.S. geopolitical policy can interrupt Synopsys's ability to serve its customers.

Beyond China, EDA and simulation tools are generally not regulated in other markets. The ITAR/EAR framework applies to sales to defense-related end users globally, but most commercial semiconductor companies are not subject to those restrictions.

Cyclicality

EDA is low-cyclicality. The industry tends to track the design cycle, not the manufacturing cycle. During a semiconductor down-cycle (2022-2023 inventory correction was the most recent), chip design spending remained elevated because chipmakers were still investing in next-generation designs. The subscription-based revenue model with multi-year contracts further dampens cyclicality: even if a chip company decides to delay a new design start, their existing tool licenses continue. The Ansys business has some exposure to industrial and automotive capex cycles, but simulation tools are generally considered essential and are not easily cut.

Section 7: Growth Triggers

Sources: Four concall transcripts - Q2 FY2025 (May 28, 2025), Q3 FY2025 (September 9, 2025), Q4 FY2025 (December 10, 2025), Q1 FY2026 (February 25, 2026)

• First integrated Ansys-EDA joint solutions expected H1 2026, including a fully integrated thermal/timing sign-off solution that allows chip designers to simultaneously optimize electronic timing and thermal behavior. Management stated these are targeted for the first half of calendar 2026. (Q3 FY2025, Sep 9; reiterated Q4 FY2025, Dec 10; reiterated Q1 FY2026, Feb 25)

"We're targeting our first set of integrated solutions in the first half of 2026 that fuse multiphysics across the full EDA stack, including for multi-die advanced packaging." (Q4 FY2025)

• Ansys revenue synergies of $400 million targeted by year four post-close (approximately FY2029), generated through cross-selling EDA tools to Ansys's non-semiconductor industrial customer base and selling Ansys simulation to Synopsys's semiconductor customers. Monetization expected to begin showing in FY2027. (Q1 FY2026, Feb 25)

• Ansys targeting double-digit organic revenue growth in FY2026, driven by subscription transition tailwind and expanded channel access through Synopsys's global salesforce. Management described the Ansys pipeline as "robust" and differentiated from EDA softness. (Q4 FY2025, Dec 10)

• NVIDIA strategic partnership - GPU-accelerated EDA and simulation on NVIDIA infrastructure, with joint go-to-market for cloud-based engineering tools. NVIDIA invested $2 billion in Synopsys common stock on December 1, 2025. The partnership includes Synopsys accelerating its compute-intensive applications on NVIDIA CUDA-X, targeting specifically chip design, electromagnetic analysis, molecular simulation, and optical simulation. Joint cloud-based offerings targeting engineering teams who cannot afford on-premise HAV hardware. (Q4 FY2025, Dec 10)

"I know we can make money. The partnership with NVIDIA is not just financial - it's about making our tools run faster and making them accessible to more customers via cloud." (Q4 FY2025)

• Hardware-Assisted Verification (HAV) growth through competitive wins - 12 competitive wins in Q4 FY2025 alone, driven by AI chip complexity demanding larger emulation capacity. ZeBu-200 and HAPS-200, launched in early 2025, were described as "off to a strong start" with customers adopting them for their AI chip verification programs. New Software-Defined HAV architecture announced Q1 FY2026 further expanding TAM. (Q2 FY2025, May 28; Q4 FY2025, Dec 10; Q1 FY2026, Feb 25)

• Sub-2nm and 2nm design wins with leading AI chipmakers - Management described in Q2 FY2025 enabling "the industry's first 2-nanometer-based HPC design" and "delivering multiple successful test chips across sub-2nm process technologies" with a leading AI chip customer. These process node wins set Synopsys as the flow of record for future advanced node designs. (Q2 FY2025, May 28)

• Multi-die 3D heterogeneous integration - Supporting production deployments with a leading HPC AI chip maker, including "the most complex 3D heterogeneous integrated design with over 40 chiplets and advanced packaging technology." The 3DIC Compiler product is positioned at the center of this trend. Management cited this as displacing manual flows with automated implementations. (Q2 FY2025, May 28)

• Agentic AI platform monetization in FY2027 - Management described development of autonomous AI agents capable of orchestrating multi-step chip design tasks, built on top of the Synopsys.ai infrastructure. With nearly 5,000 active Synopsys.ai users as of Q4 FY2025, the foundation for a new premium tier of AI-powered services is being built. Monetization is not expected in FY2026 but was flagged as a key future revenue source. (Q1 FY2026, Feb 25; Q4 FY2025, Dec 10)

• Cost structure improvement from 10% headcount reduction - Initiated in Q3 FY2025, largely complete by end of FY2026. Targeting operating margin expansion - FY2026 non-GAAP operating margin guided at 40.5% versus 38.3% in FY2025. (Q3 FY2025, Sep 9; Q4 FY2025, Dec 10)

• New royalty-based models for custom IP engagements - Management indicated pursuit of royalty revenue structures in custom IP work, where Synopsys builds bespoke IP to customer specification and retains royalty rights on chips shipped. This would convert low-margin engineering services revenue into scalable royalty income over time. (Q4 FY2025, Dec 10)

• Refocused Design IP toward high-growth protocols - The ARC processor divestiture frees resources to accelerate PCIe Gen 6, CXL, HBM3/HBM4, and UCIe interface IP development, targeting the connectivity standards driving AI chip design. Management called out "larger market potential" in these interface standards versus the processor IP market. (Q1 FY2026, Feb 25)

• Debt repayment creating financial flexibility - $2.55 billion term loan prepayment planned for FY2026, funded partly by the NVIDIA investment. Deleveraging the post-Ansys balance sheet (post-merger debt approximately $12 billion) creates room for future capital returns and investment. (Q4 FY2025, Dec 10)

Section 8: Key Risks

1. U.S. Export Control Escalation Against China

Mechanism: The U.S. government, through BIS, can at any time expand restrictions on Synopsys's ability to sell EDA software and IP to Chinese entities. In May 2025, this happened suddenly - a letter received the day after the Q2 FY2025 earnings call forced Synopsys to halt all new China orders and withdraw its full-year guidance within 24 hours. China contributed approximately 16% of FY2024 revenue and approximately 10% at the FY2025 exit rate. A permanent, comprehensive ban on EDA sales to China (covering all Chinese design companies, not just designated entities) would remove a meaningful ongoing revenue stream and impair the Design IP segment disproportionately, since China was a heavy consumer of interface IP for domestically-designed chips.

Calibration: High-probability moderate-to-significant impact. The BIS restrictions in May 2025 were rescinded within about five weeks, suggesting that EDA tools were considered less critical to national security than chip manufacturing equipment. However, the episode demonstrated that this risk is not theoretical and can materialize within hours. The assumption embedded in FY2026 guidance is "no near-term improvement" in China - i.e., management is not projecting China recovery, but is also not modeling another abrupt restriction. A re-escalation would create immediate revenue impact and guidance withdrawal.

"We assume the environment remains challenging in China, with no near-term improvement factored into our FY2026 guidance. We did experience share shift inside China as restricted customers sought local alternatives." (Q4 FY2025)

2. Ansys Integration Execution Risk

Mechanism: The $35 billion Ansys acquisition is transformational but carries substantial integration risk. The two companies had different cultures, different customer bases, and different revenue models. Synopsys is primarily a semiconductor EDA company; Ansys is a broad industrial simulation company. Integrating the salesforce - training Synopsys semiconductor salespeople to sell Ansys multiphysics tools to Boeing and Airbus, and training Ansys industrial salespeople to sell EDA tools to chip design teams - is a multi-year organizational challenge. The revenue synergy target of $400 million by year four is ambitious and depends on cross-sell success that is not guaranteed.

Additionally, the revenue model transition in Ansys (moving from upfront licenses to subscriptions in semiconductor-focused products) creates near-term revenue headwinds that, if the transition moves faster than expected, could create guidance misses. The $12 billion debt load from the acquisition constrains financial flexibility.

Calibration: Moderate probability, significant impact if the cross-sell thesis fails to materialize or if key Ansys talent is lost during integration. Ansys had deep relationships with its industrial customers that were built by specific account teams - those relationships could weaken if key people depart.

3. Design IP Structural Deterioration

Mechanism: The Design IP segment is in a multi-quarter challenging period driven by three independent factors: China export restrictions reducing design starts, a major foundry customer experiencing problems, and management acknowledging internal roadmap failures. The announced divestiture of ARC processor IP and refocus on interface IP is strategically logical but introduces transition risk. In the interim, the IP segment is operating at 23.9% operating margin versus 41.7% for Design Automation - the margin differential is large. If China does not recover, if the foundry customer situation worsens, or if the repositioned interface IP portfolio fails to ramp as expected, the IP segment could be a persistent drag on overall margins and growth.

Calibration: High-probability near-term drag, with the key question being duration. Management's mid-teens long-term growth target for IP has not been abandoned but is clearly deferred. A scenario where the IP segment grows below 5% annually for three or more years would be meaningfully below expectations.

4. Chinese Domestic EDA Capability Development

Mechanism: Chinese government and private capital are funding the development of domestic EDA tools. Companies like Empyrean Technology and Primarius Technologies are building tools that cover a subset of the design flow at older process nodes. If Chinese chip designers successfully transition to domestic tools for most of their work, Synopsys permanently loses the China opportunity even if export restrictions are lifted. Given the Chinese government's stated strategic priority of semiconductor independence, this investment will continue regardless of U.S. policy. The risk intensifies if the capability of domestic tools extends to advanced nodes.

Calibration: Low-probability near-term, medium-probability over five or more years. Current domestic Chinese EDA tools are insufficient for advanced node design at 7nm and below. But the direction of development is clear. Synopsys may be permanently impaired in China, not just temporarily restricted.

5. Agentic AI Commoditizing EDA Tool Skills

Mechanism: Synopsys is betting on AI enhancing its tools' capabilities and making them worth more. But there is an alternative scenario: AI could reduce the complexity barrier to chip design, enabling new entrants to provide acceptable design automation at lower cost. If AI makes chip design sufficiently automated that generic software companies or open-source projects can perform basic EDA tasks, the high switching costs that protect Synopsys's incumbency could erode at the margins. Google has experimented with reinforcement learning approaches to chip floorplanning that achieved results comparable to human experts.

Calibration: Low-probability, long-horizon risk. The most advanced design challenges (3nm and below, 3D-IC integration, timing closure at HPC AI chip complexity) are getting harder, not easier, and currently require the most sophisticated EDA tools available. But at simpler nodes and design styles, AI-assisted design could lower barriers.

6. Customer Concentration in AI Chip Design

Mechanism: A disproportionate share of Synopsys's growth is driven by AI chip design activity at hyperscalers and leading AI chip companies. If AI infrastructure investment stalls - due to a slowdown in AI adoption, regulatory constraints, or changes in the competitive dynamics among AI hardware vendors - EDA demand growth would decelerate. The "non-AI infrastructure" weakness mentioned consistently across concalls (automotive, industrial, consumer electronics design being subdued) means EDA growth is narrow-based in the near term.

Calibration: Moderate probability of some deceleration; the level of AI infrastructure spending in 2025 is historically exceptional and may normalize. A sharp reduction in hyperscaler AI capex would be felt in EDA and HAV demand, though the subscription model's multi-year lock-in would dampen the impact.

Section 9: Walk the Talk

Concall dates used:

1. Q2 FY2025 - May 28, 2025
2. Q3 FY2025 - September 9, 2025
3. Q4 FY2025 - December 10, 2025
4. Q1 FY2026 - February 25, 2026

The picture that emerges across these four concalls is of a management team that is mostly credible on operational delivery, stumbled on a specific external event they could not control, and has been transparent about a genuine operational misstep in the IP business while maintaining conviction in the long-term thesis.

Q2 FY2025 (May 28, 2025): Setting the Stage

In the Q2 call, CEO Sassine Ghazi (in his second year as CEO after succeeding founder Aart de Geus) described a company executing well on its core business. Design IP had surged 21% year-over-year, driven by AI/HPC demand - the strongest IP quarter in some time. Design Automation was up 6%. The Ansys acquisition was expected to close "in the first half of calendar 2025" with China regulatory approval being the last hurdle. Management reaffirmed full-year revenue guidance of $6.745-6.805 billion. When asked directly about potential BIS export restrictions on China, management stated that no formal notice had been received as of the call date.

The next day - May 29, 2025 - Synopsys received the BIS restriction letter.

This sequence deserves careful analysis. Management was technically accurate: no notice had been received as of the call. But the abruptness of the subsequent guidance withdrawal (within hours of receiving the letter) suggests the risk was not fully prepared for operationally. Synopsys had to immediately halt new China orders and suspend all financial guidance - unprecedented for a company that had provided multi-quarter visibility for years. This was not management dishonesty, but it revealed that the China export control scenario, while discussed as a risk, was not fully scenario-planned in financial guidance.

Q3 FY2025 (September 9, 2025): Acknowledging Failure

The Q3 call was the most difficult of the four. Synopsys missed consensus estimates - EPS of $3.39 versus expectations of $3.80, revenue of $1.74 billion versus $1.77 billion consensus. The export restrictions had been rescinded on July 2, but the customer behavior impact lasted well beyond the technical lifting of restrictions: customers who had questioned whether to continue multi-year Synopsys commitments during the six-week ban did not immediately resume as if nothing had happened. The Design IP segment declined 8% year-over-year.

Critically, management did something that builds long-term credibility: they did not pin the IP shortfall entirely on China. The CEO explicitly acknowledged "certain roadmap and resource decisions that did not yield intended results" - meaning Synopsys had made engineering investment decisions in the IP business that produced products customers did not want. This self-attribution of an internal mistake is not common from management teams under pressure. The 10% headcount reduction was announced simultaneously, with management explicitly connecting it to rightsizing the IP business and improving overall efficiency.

The revised FY2025 guidance of $7.03-7.06 billion was achievable from that starting point - and was indeed delivered. Q4 came in at $2.255 billion, at the high end of guidance.

Q4 FY2025 (December 10, 2025): Transformation Defined

By Q4, the story had shifted. Ansys was now fully consolidated (contributing $667.7 million in Q4 alone), backlog had grown to $11.4 billion, and NVIDIA's $2 billion equity investment had just been announced on December 1. Full-year FY2025 revenue of $7.054 billion was a record and slightly above the revised guidance range.

Management set FY2026 guidance of $9.56-9.66 billion - significantly above any prior Synopsys annual revenue and reflecting the full-year Ansys consolidation. Several specific commitments were made: the 10% headcount reduction "largely complete by end of FY2026"; Ansys double-digit growth in FY2026; first integrated Ansys-EDA solutions in H1 2026; and the Design IP segment in "muted growth" mode with long-term mid-teens potential maintained.

On China, the tone shifted from "expect challenging environment" to something more definitive: "We assume no near-term improvement." This was an appropriate reset of the China narrative - rather than perpetually promising recovery, management baked in continued weakness.

Q1 FY2026 (February 25, 2026): Execution Against the New Baseline

Q1 FY2026 came in at $2.41 billion in revenue, at the high end of guidance, with EPS of $3.77, beating guidance of $3.52-3.58 by more than 5%. The beat was driven by Design Automation strength, with HAV and EDA software showing solid demand. Management raised full-year EPS guidance to $14.38-14.46 (from $14.32-14.40 at Q4). The Ansys integration was described as "on track" with no negative surprises. Backlog remained at $11.3 billion.

Design IP declined 6% year-over-year in Q1, consistent with the "muted growth/transitional year" framing set at Q4. The ARC processor divestiture was announced, validating management's commitment to repositioning the IP portfolio. The $250M accelerated share repurchase was initiated alongside a new $1 billion buyback authorization - signaling financial confidence despite the Ansys debt load.

Assessment: This is management that hits its numbers when conditions are within its control. On the external shock (May 2025 China restrictions), the communication was technically accurate but inadequately prepared. On the internal failure (IP roadmap missteps), management proactively self-reported rather than attributing everything to external factors. The Ansys integration is proceeding without the negative surprises that are common in $35 billion acquisitions. Ghazi's first two years as CEO show a leader who sets achievable guidance and delivers on it - the miss in Q3 was real but largely external, and the response was credible. The longer-term promises (Ansys synergies by year four, agentic AI monetization in FY2027) remain future tests.

Section 10: Shareholder Friendliness Index

Dividends: Synopsys has never paid a cash dividend. Management has historically prioritized capital deployment into M&A, R&D, and share buybacks over dividends. Given the $35 billion Ansys acquisition completed in July 2025 and the resulting significant debt load (approximately $12 billion), dividend initiation is not expected in the near term. The Investor FAQ section confirms no dividend payment history.

Share Buybacks:

FY2023 (year ended October 31, 2023): Synopsys repurchased approximately $908 million of its own stock, net of option exercises, representing meaningful capital return. At the time, the company did not have the Ansys debt burden and had significant free cash flow. Multiple analysts noted this as one of the more active buyback periods in the company's recent history.

FY2024 (year ended October 31, 2024): Net equity repurchase activity declined to approximately $232 million - a sharp reduction driven by two factors: (1) the pending Ansys acquisition required Synopsys to preserve capital and comply with deal constraints, and (2) the issuance of shares in Q3/Q4 FY2024 as part of the Ansys deal structure created headwinds to net share count reduction.

FY2025 (year ended October 31, 2025): The Ansys acquisition closed July 17, 2025, with Ansys shareholders receiving 0.3450 Synopsys shares per Ansys share owned. This share issuance for the acquisition substantially increased Synopsys's share count during FY2025. The trailing twelve months buyback per share was approximately $0.90 as of October 31, 2025 - minimal relative to prior periods, as capital was consumed by the acquisition.

Post-FY2025 actions: In February 2026, Synopsys's Board approved a new $1 billion stock repurchase program. In March 2026, the company initiated a $250 million accelerated share repurchase (ASR) agreement with the Bank of Nova Scotia, with initial delivery of approximately 513,000 shares. The ASR is expected to complete by June 1, 2026. This signals management's intention to return capital and absorb dilution from the Ansys share issuance, even while managing $12 billion in acquisition debt.

Assessment: Synopsys has historically used buybacks, not dividends, as its shareholder return mechanism. The Ansys acquisition temporarily disrupted this - FY2024 and FY2025 buyback activity was materially lower due to deal constraints and debt burden. The February 2026 $1 billion authorization and March 2026 $250 million ASR represent a resumption of the buyback program, but the scale remains modest relative to the company's size and the dilution absorbed during the Ansys share issuance. Management's stated priority is debt repayment first (targeting $2.55 billion in term loan prepayments during FY2026), followed by capital return. Until the debt is materially reduced, substantial buyback programs are constrained. This is a rational capital allocation choice given the post-acquisition leverage, but shareholders received notably less buyback support in FY2024-FY2025 than the preceding years.

Section 11: Scenarios

Bull Case

In the bull case, the Ansys integration becomes the most value-creating semiconductor software acquisition of the decade. The first integrated Ansys-EDA solutions, released H1 2026 as promised, land with major semiconductor customers who immediately see the value of simultaneous electronic and physical optimization. Within two years, chip design teams at NVIDIA, Apple, and Google are using a unified Synopsys workflow from RTL design through full-system thermal and electromagnetic simulation - a workflow that Cadence and Siemens EDA simply cannot replicate. Cross-selling Ansys simulation tools into the automotive and aerospace companies already using Synopsys EDA services adds a new revenue stream with customers who previously had no relationship with Synopsys. Hyperscaler AI infrastructure spending remains strong through 2027-2028, driving continued elevated demand for EDA and HAV at advanced nodes. The NVIDIA partnership produces cloud-based EDA services that expand the total addressable market by enabling mid-tier chip designers - companies that cannot afford a $20 million ZeBu system - to access GPU-accelerated design tools at subscription rates. Design IP rebounds as PCIe Gen 6, CXL 2.0, and HBM4 interface IP drives a refresh cycle among AI chip designers. China does not get significantly worse, and the redesignation risk does not materialize. The 10% cost reduction and margin expansion deliver as guided, and Synopsys exits FY2027 with agentic AI tools generating real premium pricing. The company is a significantly more defensible, strategically broader business than it was in 2024.

Base Case

The base case is steady execution against a straightforward transformation. The Ansys integration takes time - first joint products are released as promised but adoption is gradual, with meaningful cross-sell revenue starting in FY2027 and ramping toward the $400 million synergy target by FY2029. EDA software continues growing at high-single-digit to low-double-digit rates, supported by AI chip design complexity. HAV maintains its recent competitive momentum. The Design IP segment navigates its transitional year in FY2026 and returns to mid-single-digit growth as the interface IP refresh cycle takes hold, while the ARC divestiture removes a distraction. China remains at approximately 10% of revenue - no significant improvement but no additional restriction either. The debt is repaid on schedule through free cash flow and the NVIDIA investment proceeds. Synopsys exits FY2027 as a meaningfully larger and more diversified engineering software company than before the Ansys acquisition, with improving financial metrics.

Bear Case

The bear case has multiple pressure points converging simultaneously. China export restrictions are reinstated more broadly or permanently - perhaps covering all Chinese chip design companies rather than specific entities - removing the 10% of revenue that even today's "muted" assumptions rely on, and accelerating Chinese adoption of domestic EDA alternatives that gain competency at more advanced nodes faster than expected. The Ansys integration underperforms: cultural friction and customer base differences make cross-selling harder than anticipated, key Ansys account teams depart taking relationships with industrial customers, and the revenue synergy timeline extends. The hyperscaler AI chip design boom moderates as the most aggressive phase of AI infrastructure buildout transitions to optimization - fewer new design starts, smaller HAV orders as existing emulation capacity is utilized rather than expanded. The Design IP segment continues in its depressed state as the interface IP product repositioning takes longer than expected and royalty streams from China chip shipments (which Synopsys earned on chips designed using its IP) decline. The $12 billion debt load constrains capital allocation flexibility. Synopsys is not broken - the EDA duopoly position is structurally too strong for that - but the Ansys premium embedded in expectations proves too optimistic, and the company spends several years growing into a valuation that assumed the cross-sell thesis would be delivered faster.

Sources:

• Synopsys Q1 FY2026 Earnings Call Transcript - Seeking Alpha
• Synopsys Q1 FY2026 Highlights - Yahoo Finance
• Synopsys Q4 FY2025 Earnings Call Transcript - Motley Fool
• Synopsys FY2025 Q4 Financial Results - Investor Relations
• Synopsys Q3 FY2025 Earnings Miss - Investing.com
• Synopsys Q3 FY2025 Highlights - Yahoo Finance
• Synopsys Q2 FY2025 Earnings Beat - Investing.com
• NVIDIA and Synopsys Strategic Partnership - NVIDIA Newsroom
• Nvidia $2B Stake in Synopsys - CNBC
• Synopsys Completes Ansys Acquisition - PR Newswire
• Synopsys Pulls Full-Year Guidance on China Export Restrictions - CNBC
• U.S. Lifts Chip Software Curbs on China - CNBC
• Synopsys Issues Statement on Lifting of China Export Restrictions
• Synopsys $250M Accelerated Share Repurchase - Investor Relations
• Synopsys Software Integrity Group Divestiture - News Release
• Cadence and Synopsys Duopoly Analysis - Arvy
• EDA Market Size and Growth - Precedence Research
• Synopsys DesignWare IP Portfolio
• Synopsys ZeBu and HAPS Products
• Synopsys Founding History - Wikipedia
• Synopsys TSMC Collaboration on 2D/3D Design Solutions
• China Revenue Risk to EDA Giants - TrendForce