Soitec SA (SOI.PA) - Deep Dive Research Report

Prepared: May 22, 2026 | Listing: Euronext Paris | Sector: Semiconductor Materials

Section 1: What the Company Does

Soitec makes the wafer that sits underneath the chip. Not the chip itself - the engineered starting material that every semiconductor fab receives before it begins etching transistors. Think of it as the specialized paper on which the chip is drawn. The wrong paper and the drawing falls apart; the right paper - tuned at the atomic level - is what makes the difference between a smartphone that handles 5G and one that can't, or an AI datacenter that moves light across a silicon die and one that moves electrons through copper.

The company was founded in 1992 in Bernin, a small town near Grenoble in the French Alps, by two researchers - Michel Bruel and Alain-Henri Escoffier - who had just developed something called Smart Cut at CEA-Leti, the French atomic energy commission's microelectronics lab. Their insight was this: you don't need a thick, expensive silicon ingot to make a good chip substrate. You need a very thin, perfectly uniform layer of crystalline silicon on top of an insulating oxide. If you could transfer just that thin layer from a donor crystal onto a handle wafer, you would get a substrate that was cheaper in material terms but far superior in electrical performance.

The trick for transferring a thin layer without breaking it was Smart Cut. The process works like an atomic-scale scalpel: hydrogen ions are implanted into a silicon crystal to a precise depth, creating a plane of microscopic bubbles. When the crystal is heated, those bubbles expand, and the layer above them cleaves cleanly away - like splitting a block of wood along the grain. That cleaved layer is then bonded to a handle wafer via molecular adhesion, creating a silicon-on-insulator (SOI) structure. The precision of this process - measured in fractions of a nanometer of thickness uniformity across a 300mm disk - is what makes Soitec's product fundamentally different from anything a conventional silicon supplier can offer.

The value proposition is specific and measurable. On a standard bulk silicon wafer, there is no insulating barrier between the transistor and the substrate beneath it. Current leaks. Power is wasted. Signals degrade. On an SOI wafer, the buried oxide layer acts as a perfect insulator. Electrons stay where they're supposed to. This means:

• In a smartphone radio chip, it means RF-SOI eliminates signal-stealing interference between the antenna switch and the rest of the phone, enabling simultaneous Wi-Fi, Bluetooth, and 5G without a jungle of discrete filters.
• In a 5G filter using POI (Piezoelectric-on-Insulator), it means the filter can be miniaturized to fit inside a dense RF front-end module while meeting the stringent frequency selectivity that packed carrier bands demand.
• In a silicon photonics chip for an AI datacenter, it means Photonics-SOI delivers a ~220 nanometer silicon layer on top of a 2-micron buried oxide, with thickness uniformity within one nanometer across the entire wafer, which is the exact specification needed for optical waveguides to guide light without loss.

The company employs roughly 2,200 people, operates six production lines across facilities in France and Singapore, and licenses manufacturing to Simgui (owned by China's NSIG) for the Chinese domestic market. It has accumulated more than 4,300 patents - the vast majority protecting Smart Cut and its derivatives. It invests approximately 17% of annual revenue in R&D.

In fiscal year 2025 (which ended March 31, 2025), about 61% of revenue came from the mobile communications market, 24% from Edge and Cloud AI, and 14% from Automotive and Industrial. Those proportions are in the middle of a structural shift, with the mobile share declining and the AI share expanding rapidly.

Section 2: Business Segments

2.1 Mobile Communications

This is the segment that built Soitec and is currently the segment in crisis. It encompasses three product families - RF-SOI, POI, and FD-SOI - all sold into the smartphone supply chain, which means the foundries and fabless chip companies that make the radio chips, filters, and logic that go inside Apple, Samsung, and Google phones.

RF-SOI is the original, dominant product. Every major 5G smartphone uses an RF front-end module (FEM) built on RF-SOI. The FEM handles antenna switching, power amplification, and band filtering - the electronics that negotiate between the phone's antenna and the radio protocol. RF-SOI's insulating substrate prevents the RF signals from coupling into the substrate, which would attenuate them and create cross-talk. This physical property is not replicable with bulk silicon - it requires an engineered substrate. Soitec essentially invented this market in the late 1990s and has held a dominant share since. The principal foundries making RF-SOI chips include GlobalFoundries (in Malta, New York) and Tower Semiconductor (in Migdal HaEmek, Israel). The chip makers - Skyworks, Qorvo, Murata, Broadcom - take the wafers and build FEMs for Apple, Samsung, and everyone else.

The problem for this product right now is one of inventory, not demand destruction. During 2022-2024, smartphone demand was weak, but foundries and chip makers had committed to large wafer volumes. Inventory piled up. As of the Q3 FY2026 earnings call (February 4, 2026), Soitec's RF-SOI shipments remain well below the structural demand level as customers draw down on what they already have. The correction has been deeper and longer than management initially expected.

POI (Piezoelectric-on-Insulator) is the newest and fastest-growing product in the mobile segment. It uses a piezoelectric material - lithium niobate or lithium tantalate - bonded to an insulating substrate, enabling filters with superior frequency selectivity and lower insertion loss than conventional bulk acoustic wave (BAW) or surface acoustic wave (SAW) filters. 5G smartphones need to handle dozens of frequency bands simultaneously; POI filters are becoming the standard approach for the most demanding bands above 1 GHz. As of the Q1 FY2026 call (July 23, 2025), ten customers were in volume production with POI wafers and thirteen more were in qualification. In March 2026, Soitec announced a multi-year supply agreement with Skyworks Solutions for POI wafers to serve its Sky5 5G platform - a landmark deal that publicly names a Tier 1 fabless customer.

FD-SOI (Fully Depleted SOI) is the third mobile product and the most technically sophisticated. A standard SOI structure leaves a partially depleted channel that can still suffer from transistor variability; FD-SOI makes the silicon layer so thin (approximately 6-7nm thick) that the channel is fully depleted, eliminating this variability and delivering extremely tight threshold voltage control. GlobalFoundries and Samsung both run FD-SOI process nodes. The technology has secured design wins for 5G millimeter-wave envelope trackers in premium flagship phones - Samsung Galaxy S25, Google Pixel 9, and Apple iPhone 16 all contain chips built on FD-SOI (the first two on Samsung's own FD-SOI process, the latter on GlobalFoundries' 22FDX). FD-SOI is also gaining traction in Wi-Fi 7 SoC chips, where its low-power characteristics are valuable.

Mobile Communications accounted for approximately 61% of Soitec's revenue in FY2025, making it the company's largest segment. It has been under severe pressure throughout FY2026 from the RF-SOI inventory correction, but the structural demand fundamentals - 5G densification, multi-carrier aggregation requiring more filters, growing FD-SOI penetration in premiums - remain intact.

2.2 Automotive and Industrial

This segment serves the power electronics market - specifically the chips that manage current flow in electric vehicles, industrial drives, and power conversion equipment. It has two product families.

Power-SOI integrates high-voltage and low-voltage functions on a single chip, which is critical for the gate drivers, power management ICs, and battery management systems in modern vehicles. The buried oxide in Power-SOI acts as an isolation barrier between the high-voltage power domain and the low-voltage logic domain, enabling "smart power" integration that would cause substrate coupling failures on bulk silicon. The automotive supply chain here runs through Tier 1 chipmakers including Renesas, Infineon, ON Semiconductor, and STMicroelectronics.

SmartSiC is Soitec's engineered silicon carbide substrate. Silicon carbide is the material of choice for the main power inverter in electric vehicles because it handles high voltage and high temperature far better than silicon. Soitec's twist on conventional SiC was to apply its Smart Cut process to create a bonded SiC-on-insulator structure, which it argues enables thinner epitaxial growth (saving expensive SiC epi material) and better wafer quality. However, this bet has not gone as planned. In H1 FY2026, Soitec took a €41 million impairment on its SmartSiC non-current assets, acknowledging that the market opportunity is materially smaller than assumed when the Bernin 4 manufacturing facility was built. The reason is twofold: EV demand has grown more slowly than projections, and Chinese SiC manufacturers (including substrates from SICC, HiWafer, and TYSiC backed by BYD) have aggressively commoditized the substrate market, making it hard for Soitec's premium-priced engineering approach to find enough customers.

Automotive and Industrial was approximately 14% of FY2025 revenue and has been the weakest segment in FY2026 - falling more than 70% in H1 FY2026 as inventory corrections and EV demand softness combined. The segment's trajectory is the key uncertainty in Soitec's medium-term story: Power-SOI recovery depends on automotive inventory normalization, while SmartSiC's future is now an open question after the impairment.

2.3 Edge and Cloud AI

This is the smallest segment today but the highest-conviction growth story. It covers two distinct end markets with very different products.

Photonics-SOI is the segment's crown jewel and the product Soitec has a near-monopoly on. Silicon photonics uses optical components - waveguides, modulators, detectors - fabricated using standard semiconductor processes on an SOI substrate. The key enabling material is a specific flavor of SOI: approximately 220nm of crystalline silicon on 2 microns of buried oxide, with thickness uniformity of ±1nm or better across the entire wafer. This specification cannot be met with bulk silicon and essentially cannot be met by any competitor at volume because Soitec is the only company with both the Smart Cut technology and the years of process refinement needed to hit these tolerances at yield.

The application that's driving demand is AI optical interconnects. Modern AI chips are so fast at matrix multiplication that the bottleneck has moved to moving data in and out. Copper wires at the speeds needed (800G, 1.6T per second) generate too much heat and signal loss. Optical transceivers solve this, but traditional transceivers plug into the edge of the chip package and still require copper between the optical engine and the switch ASIC. Co-packaged optics (CPO) goes further: the optical engine is placed directly inside the package, reducing the copper path to millimeters. CPO requires far more silicon photonics real estate per port than a pluggable transceiver - roughly four times more. NVIDIA announced its first CPO products (Spectrum-X and Quantum-X) in March 2025. Broadcom, Intel, and Marvell had been building CPO roadmaps since 2023. Every silicon photonics chip in every one of these products requires Photonics-SOI substrate. The primary foundries making silicon photonics chips - Tower Semiconductor, TSMC, GlobalFoundries - all qualify and use Soitec's Photonics-SOI. As of mid-2026, no other supplier has qualified at these foundries for photonics applications.

FD-SOI in edge applications is the second growth engine in this segment. FD-SOI's low power consumption makes it attractive for IoT devices, AI inference at the edge, and any application where battery life or thermal envelope is constrained. FD-SOI chips for edge AI are manufactured primarily at Samsung and GlobalFoundries. The segment also previously included Imager-SOI (a substrate for near-infrared image sensors used in AR/VR and Face ID), but Soitec discontinued this product in FY2026 as the market did not develop as expected.

An emerging third application in this segment is quantum computing. In February 2026, Quobly - a French quantum computing startup - announced it had achieved a meaningful milestone fabricating a quantum processor on 28Si FD-SOI wafers at STMicroelectronics' 300mm fab. Soitec supplies the silicon-28 (isotopically purified) FD-SOI wafers for this work. This is not material to near-term revenue but is the kind of long-duration option that the FD-SOI platform creates.

Edge and Cloud AI was approximately 24% of FY2025 revenue, growing 11% that year while every other segment declined. In FY2026 it has maintained momentum, with Photonics-SOI delivering strong growth even as the segment is partially dragged by the Imager-SOI discontinuation.

Segment summary comparison:

Section 3: Products and Business Detail

The Smart Cut Process

Everything at Soitec starts with Smart Cut. Understanding it is essential to understanding why the company has a moat.

Step 1: A donor wafer - a standard silicon or compound semiconductor crystal - undergoes hydrogen ion implantation. Hydrogen ions are accelerated to a precise energy level and shot into the crystal. The energy determines the depth at which the ions stop. This depth, measured in nanometers, defines exactly where the cleave will occur. The density of implanted ions creates a buried plane of hydrogen-rich defects.

Step 2: A handle wafer - usually silicon, but for photonics applications it's a thermally grown oxide on silicon - is cleaned and surface-activated using plasma treatment to create reactive bonds.

Step 3: The donor wafer and handle wafer are bonded face-to-face at room temperature using van der Waals molecular adhesion. No adhesive. Just perfectly flat, ultra-clean surfaces brought into contact.

Step 4: The bonded pair is annealed at moderate temperature (typically 500°C). The hydrogen ions in the donor wafer coalesce and the bubbles grow. At a critical threshold, the thin layer above the implant plane cleaves away cleanly. The donor wafer's surface below the cleave point is polished and reused.

Step 5: The transferred layer is polished to nanometer-level smoothness. The result is a precisely defined crystalline layer, perfectly bonded to the handle wafer, with controlled thickness and uniformity.

The process refinement built up over 30+ years cannot be replicated quickly. Yield, uniformity, defect density, and throughput are all process-maturity dependent. A competitor with the same fundamental chemistry would need years of learning cycles to achieve the same specifications. Soitec's 4,300+ patents protect not just the core Smart Cut concept but the hundreds of process variations, tool modifications, and quality control methods developed through industrial production.

Product Catalogue

RF-SOI: The dominant product by historical volume. A 300mm wafer with a 70-100nm silicon device layer on a buried oxide. RF-SOI wafers are sold to foundries (GlobalFoundries, Tower Semiconductor, WIN Semiconductors) who use them as starting material for RF front-end chips. The chip makers (Skyworks, Qorvo, Murata, Broadcom) are the foundries' customers who buy the finished chips. Soitec sells to the foundry, not directly to the chip maker.

POI (Piezoelectric-on-Insulator): A more advanced bonded structure using lithium niobate (LiNbO3) or lithium tantalate (LiTaO3) as the piezoelectric layer, bonded via Smart Cut to a silicon substrate with an insulating layer. The piezoelectric material handles acoustic wave propagation for RF filtering; the insulating substrate prevents energy from leaking into the substrate. POI enables filters with lower insertion loss and higher power handling than conventional SAW or BAW filters. As of Q1 FY2026 (July 2025), Soitec has ten customers in production and thirteen in qualification for POI - the broadest POI customer base in the industry. The multi-year Skyworks deal (March 2026) confirms that POI is crossing from early-adoption to mass-market deployment.

FD-SOI: The thinnest product in the portfolio, with a silicon layer of approximately 6-7nm on a buried oxide of approximately 25nm. The critical parameter is uniformity - variations in silicon layer thickness translate directly into variability in transistor threshold voltage, which is the problem FD-SOI was designed to solve. GlobalFoundries' 22FDX and 12FDX nodes and Samsung's 28FDS and 14FDS nodes all use Soitec FD-SOI wafers as starting material.

Photonics-SOI: Soitec's fastest-growing and most strategically important product. The specification - approximately 220nm silicon layer on 2 microns of buried oxide, ±1nm thickness uniformity - is not a target specification; it is a physical requirement for optical waveguide performance. Silicon photonics waveguides work because light travels in the silicon layer guided by total internal reflection against the oxide boundary. If the silicon layer thickness varies by more than a few nanometers, the waveguide modes change, and the circuit doesn't work. This is the specification that Soitec has spent two decades developing the process to hit consistently, and which no competitor has demonstrated the ability to match at production volumes. Photonics-SOI is manufactured at Soitec's Bernin facility and sold to Tower Semiconductor, TSMC, and GlobalFoundries as foundry starting material. The end products include AI datacenter optical transceivers, co-packaged optics switches, and LiDAR sensors.

Power-SOI: A thicker structure designed for automotive and industrial applications, with silicon layers ranging from a few hundred nanometers to several micrometers. Power-SOI's defining feature is its ability to integrate both high-voltage and low-voltage components on the same chip without latch-up or substrate coupling. Customers include Renesas, Infineon, STMicroelectronics, and ON Semiconductor.

SmartSiC: Silicon carbide substrate using Smart Cut to transfer a thin SiC layer. Intended for EV power inverter applications. Currently in customer qualification (five customers per management commentary) but commercially behind plan. The impairment taken in H1 FY2026 reflects a revised market sizing. The product has received some interest for data center power supply (UPS) applications, where the premium performance justifies the cost, but these volumes are not imminent.

PD-SOI and MEMS-SOI: Smaller product lines for high-performance computing (IBM has historically used PD-SOI for its POWER processors) and MEMS sensors. Not primary growth drivers.

Manufacturing Geography

Soitec's primary manufacturing hub is Bernin, France, near Grenoble. There are three production facilities there:

• Bernin 1: RF-SOI and legacy products
• Bernin 2: Advanced products, newer wafer sizes
• Bernin 4: SmartSiC (built 2022-2024, currently underutilized)

A facility in Singapore handles FD-SOI pilot production and some specialty products. In China, Simgui (owned by NSIG) operates 200mm SOI wafer production under a Soitec technology license, manufacturing RF-SOI and Power-SOI for the Chinese domestic market. Soitec manages worldwide resale of Simgui product, and in March 2026, extended the NSIG/Simgui licensing framework for another 10 years - with no new technology transfer and a joint commitment to protect Soitec's intellectual property rights in China.

Section 4: Customers

Soitec sits in the semiconductor value chain as a material supplier to foundries. This means Soitec's direct customers are not Apple, NVIDIA, or Broadcom - they are the fabs that process silicon photonics wafers, RF chips, and power ICs. The end-customer dynamics, however, matter just as much because they ultimately drive wafer demand.

The foundry customer model: The buying process for engineered substrates typically unfolds at two levels. First, the end-chip company (say, Skyworks making an RF filter) works with Soitec to qualify the substrate for their specific process. This qualification can take 12-24 months and involves extensive testing to validate that Soitec's wafer meets the chip company's parametric requirements for carrier mobility, threshold voltage, RF isolation, or optical mode confinement. Once qualified, the chip company specifies Soitec as the approved substrate supplier in their process design kit. Then the foundry buys wafers from Soitec to make chips for that customer. This creates a direct connection between Soitec and the chip company even though the commercial relationship runs through the foundry.

Switching costs: Switching costs are structural and extremely high. A foundry that has qualified Soitec's photonics-grade SOI for its silicon photonics process cannot simply switch to a different wafer supplier without re-qualifying its entire process flow - a process that takes 12-24 months and requires that a qualified alternative supplier actually exists. In photonics-SOI, no qualified alternative volume supplier exists today. In RF-SOI, the switching cost is real but not absolute - Shin-Etsu and NSIG/Simgui have produced qualified RF-SOI for some foundries, but Soitec's higher performance and consistency give it an advantage in design wins for advanced nodes.

Named customers and relationships:

• Tower Semiconductor is Soitec's largest Photonics-SOI customer and a critical partner for the AI datacenter thesis. Tower's silicon photonics revenue grew over 100% in 2025 and Tower announced plans to grow its photonics foundry capacity approximately 5x between year-end 2025 and year-end 2026. More than 70% of Tower's expanded capacity has reportedly been pre-reserved by customers through 2028. Every wafer Tower runs in its silicon photonics process uses Soitec Photonics-SOI as starting material.

• GlobalFoundries is Soitec's largest FD-SOI and a significant RF-SOI customer. GlobalFoundries runs FD-SOI at its Malta, NY fab and RF-SOI at multiple sites. Management has cited winning FD-SOI share at GlobalFoundries for 5G mmWave components.

• Samsung runs FD-SOI at its Hwaseong fab in South Korea. Samsung's FD-SOI process has been adopted for mmWave chips in Google Pixel phones and for envelope trackers in various 5G flagship devices. Samsung purchases FD-SOI wafers from Soitec.

• Skyworks Solutions is the largest RF front-end module company by revenue and produces chips on Soitec's RF-SOI and POI wafers. The March 2026 multi-year POI agreement for the Sky5 platform is the highest-profile named customer relationship in Soitec's recent history and signals that POI is transitioning from qualification-phase to high-volume production at the world's largest filter manufacturer.

• Qorvo is the other major RF FEM company and also uses RF-SOI substrate via its foundry partners.

• Infineon, STMicroelectronics, Renesas, ON Semiconductor: All qualified users of Power-SOI for automotive and industrial power management ICs.

Customer concentration: Soitec does not disclose customer concentration by name. The foundry model means that a small number of major foundries - Tower, GlobalFoundries, Samsung, TSMC, and a handful of others - represent the bulk of direct purchases. Within photonics-SOI, Tower Semiconductor's ramp represents a disproportionate share of growth. This creates a concentration dependency: Tower's capacity expansion plans, qualification timelines, and customer relationships substantially shape Soitec's photonics revenue trajectory.

Section 5: Competitive Landscape

The semiconductor substrate market is not like most markets. The number of qualified participants in each sub-market is tiny, switching costs are high, and the learning curve in process technology creates durable advantages. The competitive dynamics differ significantly by product.

RF-SOI and Power-SOI

In RF-SOI, Soitec competes primarily with:

• Shin-Etsu Chemical (SEH): The world's largest silicon wafer company by volume. SEH holds a royalty license to Smart Cut (signed in 1997) and produces RF-SOI wafers, primarily for the Japanese supply chain. SEH's scale in bulk silicon gives it a cost advantage in commodity wafers, but its RF-SOI process has not been the specification leader. SEH does not compete meaningfully in photonics-grade SOI.

• SUMCO Corporation: Japan's second-largest silicon wafer maker. SUMCO has SOI capabilities but has not been a major commercial force in the engineered substrate segments where Soitec competes.

• NSIG/Simgui: China's state-backed National Silicon Industry Group owns Simgui, which manufactures 200mm RF-SOI and Power-SOI wafers at its Shanghai facility under a Soitec technology license. Simgui serves the Chinese domestic market and sells globally only through Soitec. The 10-year extension of the licensing framework (March 2026) preserves this structure with no new technology transfer - Soitec gets royalties and retains control of global distribution, while Simgui gets continued access to Smart Cut processes for 200mm wafers. This is not a competitive threat; it is a managed relationship that gives Soitec a China manufacturing presence without giving away the crown jewels.

• GlobalWafers: The world's third-largest silicon wafer maker, GlobalWafers had a Smart Cut license that Soitec terminated in October 2023. The parties reached a settlement in July 2025, giving GlobalWafers a transition period until June 2027, after which they exit the SOI wafer market entirely. The termination signals that Soitec was sufficiently confident in the enforceability of its IP to take on a major global supplier - and won.

Photonics-SOI

This is where the competitive picture is most dramatic. Bank of America estimates Soitec's share of photonics-grade SOI at above 95%. The practical reality: Soitec is the only qualified volume supplier to any major silicon photonics foundry. GlobalWafers attempted to compete but is exiting. Shin-Etsu holds a royalty license but sells no meaningful photonics volume. China's Simgui does not supply photonics-grade SOI (not included in the Soitec/NSIG licensing framework for 200mm wafers, and photonics applications require 300mm wafers which Simgui does not make).

Why is Soitec's Photonics-SOI monopoly so durable? Several reinforcing factors:

1. Specification difficulty. Achieving ±1nm silicon layer uniformity at 220nm target thickness across a 300mm wafer, at production yield and throughput, requires a process refinement level that competitors simply have not accumulated.

2. Foundry qualification lock-in. Tower, TSMC, and GlobalFoundries have each spent years qualifying their photonics processes on Soitec substrate. The process design kit is built around Soitec's specific wafer characteristics. Re-qualification with a new supplier would take 18-24 months minimum and requires a supplier who can actually meet the specification.

3. Smart Cut IP. While the foundational patent has expired, the 4,300 process patents around it - and the successful enforcement against GlobalWafers in 2023-2025 - demonstrate that Soitec can enforce its IP position.

4. Demand is growing faster than any competitor could build capacity. By the time a competitor developed a qualified photonics-SOI process, the market will be significantly larger and Soitec will have further entrenched its position.

SmartSiC

Here, the competitive position is materially weaker. Soitec competes in silicon carbide substrates against:

• Wolfspeed (US, dominant SiC substrate and wafer supplier)
• Coherent Corp (formerly II-VI) (US/global SiC substrates and epi)
• STMicroelectronics (developing internal SiC supply)
• Chinese suppliers (SICC, HiWafer, TYSiC backed by BYD) - rapidly scaling, aggressively priced

SmartSiC's differentiation - applying Smart Cut to SiC for thinner epi and better substrate quality - has not been sufficient to overcome the pricing pressure from Chinese monocrystalline SiC and the slower-than-expected EV demand environment. The impairment taken in H1 FY2026 reflects a realistic reassessment of this competitive position.

POI

Soitec has the strongest competitive position in POI relative to its starting scale. The technology is nascent enough that customers have fewer pre-established alternatives. The main competitive dynamic to watch is whether Murata (via its acquisition of Resonant and continued MEMS filter development) develops a competing substrate technology that doesn't require Soitec's POI. As of mid-2026, no competing substrate approach has demonstrated the same performance at cost in high-volume production, and Soitec's base of 10 volume customers and 13 in qualification reflects a technology that is winning design-ins before alternatives are available.

Section 6: Industry

What Drives Demand

Soitec's products sit at the intersection of three major technology megatrends: 5G densification, energy efficiency in computing, and artificial intelligence.

5G drives demand for RF-SOI and POI. Each generation of wireless increases the number of frequency bands a handset must support simultaneously. 5G NR uses more carrier aggregation than 4G, requires wider bandwidth components, and adds mmWave bands in many markets. Each new band needs more sophisticated filtering and switching. RF-SOI's isolation properties are the enabling substrate for the antenna switches and FEMs that manage this complexity. POI takes it further for filter applications. The shift from 4G to 5G essentially mandates more engineered substrate content per phone.

Energy efficiency drives Power-SOI and FD-SOI. Automotive electrification requires power electronics that can handle high voltages with minimal heat dissipation - Power-SOI's integration advantage addresses this. FD-SOI's low leakage current makes it attractive for any battery-powered application where standby power matters.

Artificial intelligence drives Photonics-SOI. AI model training and inference require moving vast amounts of data between chips and between servers at very high speed. Optical interconnects are displacing copper at the most bandwidth-intensive links. Co-packaged optics represents the next step: integrating optical engines directly into switch packages, quadrupling the silicon photonics area per port relative to pluggable transceivers. Every silicon photonics chip in this ecosystem requires Soitec's Photonics-SOI substrate.

Industry Size and Growth

The global SOI wafer market was valued at approximately $1.2 billion in 2023 and is projected to grow at roughly 10% annually, reaching approximately $2.3 billion by 2030. Within that, the photonics-SOI subsegment - currently small in absolute terms - is the fastest growing at roughly 24% annually through 2030. The silicon photonics end-market, to which Photonics-SOI is the enabling substrate, was approximately $3.1 billion in 2025 and is expected to reach $10+ billion by 2030 at a 27% compound growth rate.

Management's own framing of the addressable market is in wafer units: from approximately 5 million 200mm-equivalent wafers in 2024 to approximately 12 million by 2030. That doubling-plus of addressable volume over six years represents the aggregate demand from expanding 5G penetration, growing FD-SOI adoption in edge AI, and the emerging photonics-SOI market.

Supply Chain Position

Soitec is two steps upstream from the end consumer:

• Raw silicon / compound semiconductor materials (from REC Silicon, Wacker, Shin-Etsu)
• → Soitec (engineers the substrate)
• → Silicon photonics / RF foundries (process chips on Soitec wafers)
• → Chip companies (Skyworks, Broadcom, NVIDIA, etc.)
• → OEMs (Apple, Samsung, hyperscalers)
• → End users

This position gives Soitec pricing power in specialty segments (Photonics-SOI, POI) because there is no substitute, but exposure to cyclicality in commodity-adjacent segments (RF-SOI, Power-SOI) because inventory builds and corrections at the foundry and chip level cascade back to substrate demand.

Cyclicality

The mobile segment showed the downside of cyclicality starkly in FY2026. RF-SOI inventory at Soitec's foundry customers built up over 2022-2024 and required roughly 12-18 months to burn down. During the correction, Soitec's actual shipments fell far below structural demand. The photonics segment is less cyclical because it is in a demand-constrained early growth phase - customers want more wafers than Soitec ships, not fewer.

Regulation and Geopolitics

France has classified semiconductor manufacturing as strategic infrastructure. Soitec benefits from French government support (it received financing from the European Investment Bank for R&D investments) and is included in the broader European push for semiconductor self-sufficiency under the EU Chips Act. The China dimension is carefully managed: Soitec licenses its 200mm SOI technology to NSIG/Simgui for China's domestic market but retains control of 300mm technology (including Photonics-SOI). This structure limits technology leakage to China while maintaining access to Chinese domestic demand.

Section 7: Growth Triggers

Concalls used: FY2025 Full Year (May 27-28, 2025); Q1 FY2026 Revenue Update (July 22-23, 2025); H1 FY2026 Results (November 19-20, 2025); Q3 FY2026 Revenue Update (February 3-4, 2026). All four are the most recent reporting events prior to May 22, 2026. Full-year FY2026 results are due May 27, 2026 and are not yet published.

• Photonics-SOI demand ramp from AI datacenter build-out. Management cited strong Photonics-SOI momentum in every single concall over the four periods. Tower Semiconductor - Soitec's anchor photonics customer - announced a 5x capacity expansion in silicon photonics between year-end 2025 and year-end 2026, with over 70% pre-reserved by customers through 2028. This directly translates to Soitec wafer demand. (Repeated across all four concalls, most recently Q3 FY2026, February 4, 2026)

• Co-packaged optics commercialization driving 4x more wafer area per port. Management highlighted the CPO transition in multiple calls. NVIDIA's first CPO products (Spectrum-X and Quantum-X) were unveiled in March 2025. A CPO switch module uses approximately four times the Photonics-SOI area of a pluggable transceiver. As CPO penetration grows from a small base today toward mainstream deployment in the 2027-2028 timeframe, Soitec's revenue per AI port served would grow even without an increase in port count. Soitec joined the SEMI Silicon Photonics Industry Alliance (SEMI SiPhIA) alongside TSMC and ASE as advocates in 2025. (FY2025 Full Year, May 2025; H1 FY2026, November 2025)

"CPO enables around 30% energy saving compared with current optical transceiver-based solutions." - Soitec, March 2026 press release on CPO contributions.

• POI becoming the industry standard for 5G filters. From one customer in production at the FY2025 Full Year call to ten in production and thirteen in qualification by Q1 FY2026 (July 2025). The multi-year Skyworks deal for its Sky5 platform (announced March 2026) is the highest-profile commercial confirmation of this trend. Management described POI as "becoming standard for innovative smartphones." (All four concalls; Skyworks deal announced post-Q3 FY2026)

• RF-SOI inventory correction nearing an end. Management described the correction as "ongoing" in each of the last four calls but noted in Q3 FY2026 (February 4, 2026) that mobile communications would "improve sequentially" in Q4 FY2026. Q4 FY2026 guidance of approximately 20% sequential growth was partly premised on mobile inventory corrections progressing. A return to structural RF-SOI demand levels would represent a significant volume recovery for Soitec's largest-by-history product. (Q3 FY2026, February 4, 2026)

"While Q3'26 revenue came in above guidance, driven by solid performance by Soitec's teams, we are maintaining our prudent stance." - Pierre Barnabé, CEO, Q3 FY2026 concall, February 4, 2026.

• FD-SOI design wins in flagship phones driving next-generation ramp. Samsung Galaxy S25, Google Pixel 9, and Apple iPhone 16 all contain FD-SOI-based components. Additional design wins for Wi-Fi 7 SoCs for premium Android smartphones were cited at H1 FY2026 (November 2025). As these design wins transition to volume production and as the FD-SOI ecosystem expands (mmWave, Wi-Fi 7, potential cybersecurity applications with CEA-Leti), structural FD-SOI demand grows. (Q1 FY2026 and H1 FY2026 concalls)

• PSMC Transistor Layer Transfer collaboration (TLT technology). In July 2025 (Q1 FY2026 call), Soitec announced a strategic collaboration with PSMC, a Taiwanese foundry, on TLT technology. TLT is a next-generation substrate engineering technique that could extend the Smart Cut concept to advanced logic process nodes by enabling the transfer of fully processed transistor layers from one substrate to another. This is a long-duration R&D trigger but validates that Soitec is expanding its Smart Cut know-how into chiplet integration architectures. (Q1 FY2026, July 2025)

• FD-SOI cybersecurity applications with CEA-Leti. Also announced at Q1 FY2026, Soitec and CEA-Leti (its founding research institution) initiated a strategic partnership on FD-SOI substrates for cybersecurity chip applications. This opens FD-SOI to a new vertical where performance characteristics - particularly the ability to implement physically unclonable functions and side-channel attack resistance - are valued. (Q1 FY2026, July 2025)

• SmartSiC data center UPS opportunity. While management downgraded its EV market expectations, the H1 FY2026 call (November 2025) noted "growing interest in SmartSiC's ability to enhance power supply efficiency in next-generation data centers." Data center UPS systems are high-power applications where SiC's performance advantages are clear and where pricing is more forgiving than automotive. This is not near-term but represents a potential pivot for the SmartSiC asset. (H1 FY2026, November 2025)

• Addressable market expansion from 5 million to 12 million 200mm-equivalent wafers by 2030. Management's framing of the long-term market opportunity, stated at the FY2025 Full Year results call (May 2025), implies a structural demand doubling-plus over six years that provides a strong tailwind for all product segments. (FY2025 Full Year, May 2025)

• New organizational structure around five product lines (announced H1 FY2026, November 2025). Soitec restructured from a customer-segment organization into five product-focused operating units. This is designed to accelerate product-line accountability, innovation cycles, and customer responsiveness as the portfolio diversifies away from its historical RF-SOI concentration. (H1 FY2026, November 2025)

Section 8: Key Risks

1. RF-SOI inventory correction is longer and deeper than management has consistently guided. The mechanism: if foundry customers accumulated excess inventory during 2022-2024 and are burning it down rather than ordering new wafers, Soitec's revenue is structurally depressed. Each quarter in which customers prefer to use existing inventory rather than order new wafers costs Soitec revenue it cannot recover. Management has called the "end" of the correction at various points across the four concalls, but the timeline has repeatedly slipped. Through Q3 FY2026, mobile revenue was still deeply below prior-year levels. The risk is that the correction extends into FY2027, particularly if smartphone market volumes are weaker than expected or if China's domestic RF chip production reduces demand for Soitec's output from Western foundries. This is a moderate-probability, moderate-duration risk that has already hurt materially.

2. SmartSiC is structurally impaired by Chinese competition and EV demand disappointment. The mechanism: Soitec built Bernin 4 on a projection of SiC substrate demand driven by European and North American EV adoption. Both assumptions have partially failed - EV growth has been slower than projected and Chinese SiC suppliers (TYSiC, SICC, HiWafer) have commoditized the bulk monocrystalline SiC substrate market with aggressive pricing. Soitec's premium-engineered SmartSiC struggles to justify its cost unless customers pay up for the performance advantage. The €41 million impairment in H1 FY2026 acknowledges this but does not fully write down the SmartSiC investment. Additional impairments or a strategic exit from the SmartSiC business are plausible if no major automotive customer qualifies the product in the next 12-24 months. This is a high-probability moderate impact risk - not existential (SmartSiC is a small share of revenue) but a capital allocation mistake with ongoing carrying costs.

3. Photonics-SOI customer concentration - Tower Semiconductor dependency. The mechanism: Tower Semiconductor is expanding its silicon photonics capacity 5x and pre-reserving it through 2028. This is overwhelmingly positive for Soitec's near-term photonics revenue. But it also means Tower is becoming Soitec's largest single photonics customer. If Tower's silicon photonics ramp is delayed, its customers (transceiver makers, CPO companies) slow orders, or Intel's acquisition attempts or competitive dynamics alter Tower's foundry strategy, Soitec's photonics revenue could be materially impacted even while the underlying AI market remains strong. This is a low-to-moderate probability risk but with high impact given how central Tower is to Soitec's growth story.

4. CEO transition introduces execution uncertainty. The mechanism: Pierre Barnabé, who led Soitec through the 5G transition, the portfolio diversification strategy, and the FY2026 downcycle, departed on March 31, 2026. Laurent Rémont, former Senior VP at Infineon (where he ran the Radio Frequency and Sensors business) and former CTO at Kontron, joined as CEO on April 1, 2026. Rémont brings relevant RF background but is new to the company. The risk is that he revises strategy in ways that unsettle the product roadmap, that the organizational restructuring (into five product lines) takes longer to bed in than expected, or that key technical staff are lost during the transition. This risk is moderate probability / low-to-moderate impact.

In the Q3 FY2026 concall (February 4, 2026), Barnabé described the appointment as marking "Soitec's entry into a new growth phase supported by diversification and R&D investment" - framing the transition as strategic, not reactive.

5. FD-SOI vs. bulk FinFET competition. The mechanism: FD-SOI competes with bulk FinFET as a process architecture for mobile and edge applications. TSMC's and Intel's leading-edge nodes are all FinFET/Gate-All-Around based. If Samsung and GlobalFoundries (the main FD-SOI foundries) lose market share to TSMC and Intel for the application categories where FD-SOI competes, demand for FD-SOI wafers falls. The risk is partly technological - FD-SOI has argued power efficiency advantages that matter at edge - and partly commercial: whether TSMC's or Intel's process wins more design-ins in the FD-SOI addressable applications. This is a slow-moving but real competitive risk for the FD-SOI product line.

6. China geopolitical risk affecting NSIG partnership. The mechanism: Soitec licenses technology to NSIG/Simgui for Chinese domestic manufacturing. If US or EU export controls on semiconductor technology are extended to cover SOI substrate technology, Soitec could be required to terminate or modify this arrangement, losing royalty income and potentially losing the China SOI market to Chinese competitors who develop indigenous processes. The March 2026 10-year framework extension notably includes "no new technology transfer" language - consistent with Soitec managing this risk proactively. But the risk of export control escalation is real and depends on geopolitical developments beyond Soitec's control.

7. Photonics-SOI spec tightening as CPO advances. The mechanism: current CPO architectures use the same photonics-SOI specification that Soitec supplies today. Next-generation co-packaged optics may require even tighter silicon thickness uniformity or novel substrate configurations (e.g., silicon on sapphire for thermal management). If the specification evolves to something Soitec cannot yet produce in volume, a competitor who develops the new spec could win next-generation design-ins. This is a long-duration, lower-probability risk but is the primary technical threat to Soitec's photonics monopoly.

Section 9: Walk the Talk

Concall dates used:

1. FY2025 Full Year Results - May 27-28, 2025
2. Q1 FY2026 Revenue Update - July 22-23, 2025
3. H1 FY2026 Results - November 19-20, 2025
4. Q3 FY2026 Revenue Update - February 3-4, 2026

The most recent concall was on February 4, 2026, which is 107 days before today. The full-year FY2026 results call is scheduled for May 27, 2026 - five days away and not yet available.

The clearest thing you can say about Soitec's management across these four concalls is this: they have been consistently conservative in their guidance and have delivered at or above each quarter's specific target. The broader admission at the FY2025 Full Year call - withdrawing all annual guidance entirely - was itself a form of management honesty rather than concealment.

Starting with FY2025 Full Year (May 2025): Pierre Barnabé opened with a direct acknowledgement: guidance withdrawn entirely due to "reduced visibility and market uncertainties." For Q1 FY2026 specifically, he guided revenue would be down "around 20% year-on-year" at constant FX. He did not dress this up.

"We closed fiscal year 2025 in line with our revised guidance, with strict cost management enabling robust EBITDA margin and positive free cash flow, and continue investing both in innovation and in industrial capacity." - Barnabé, FY2025 Full Year call, May 2025.

The FY2025 annual outcome was indeed in line with the revised guidance that had been provided at the FY2024 results call - suggesting management had reset expectations accurately during a downcycle rather than maintaining stale optimism.

Q1 FY2026 (July 2025): Against the -20% year-on-year guidance provided at the prior call, Q1 FY2026 came in at -16% organically. Beat. Management guided Q2 FY2026 would grow "approximately 50%" sequentially on an organic basis. Capital expenditure for FY2026 was confirmed at approximately €150 million, down sharply from the prior year.

"Q1'26 revenue was slightly better than guidance, down 16% year-on-year on an organic basis." - Barnabé, Q1 FY2026 call, July 2025.

H1 FY2026 (November 2025): Q2 FY2026 came in at +47% sequentially on an organic basis against the guided ~50%. The narrowly missed target is worth noting - this is the one period in the four where Soitec missed the absolute guidance, and the miss was modest (47% vs. 50% sequential growth). More notable was management's Q3 guidance: "mid-to-high single-digit sequential growth" on an organic basis.

"Q2'26 performance was in line with our expectations, demonstrating strong momentum in Edge & Cloud AI, continued inventory correction in Mobile Communications, and a lackluster Automotive market." - Barnabé, H1 FY2026 call, November 2025.

Also at this call: the €41 million SmartSiC impairment was disclosed, Barnabé's departure was announced, the organizational restructuring was described, and capital expenditure guidance for FY2026 was reduced further from €150 million to approximately €140 million. This was a materially negative call in terms of news flow - but all the bad news was disclosed clearly, not buried.

Q3 FY2026 (February 2026): Against the "mid-to-high single-digit" sequential growth guidance from November 2025, Q3 FY2026 came in at +18% sequentially. A massive beat - nearly double the high end of guidance. Management's response was characteristically measured: "maintaining our prudent stance."

"While Q3'26 revenue came in above guidance, driven by solid performance by Soitec's teams, we are maintaining our prudent stance." - Barnabé, Q3 FY2026 call, February 4, 2026.

Q4 FY2026 was guided at approximately 20% sequential growth, again on a constant-FX basis.

The pattern across four calls: Management has set a low bar and cleared it three out of four quarters. The one miss (Q2 FY2026 at 47% vs. 50% guided) was narrow and the miss was in the opposite direction to what investors feared - the business was doing better than feared in Q1, at guidance in Q2, and significantly better than guidance in Q3. The SmartSiC impairment was a clear acknowledgement of a strategic mistake. The guidance withdrawal at FY2025 Full Year was an honest read of visibility rather than optimistic spin.

Promise vs. Outcome Table:

The verdict: management consistently sandbags and delivers at or above guidance. This is a positive credibility pattern. Soitec's guidance framework under Pierre Barnabé was conservative by design, setting expectations low enough to beat rather than promising aggressively. The one cautionary note is that withdrawing guidance entirely (FY2025 Full Year call) means the longer-term narrative - addressable market doubling by 2030, Photonics-SOI sustained high growth - should be treated as directional rather than contractual. The track record on near-term guidance is strong; the longer-term market sizing statements have not yet been tested against outcomes.

Section 10: Shareholder Friendliness Index

Dividends: Soitec has not paid a dividend since February 2017 - nearly a decade of zero distributions to shareholders. No dividend was paid for FY2023, FY2024, or FY2025. Each year's Annual General Meeting has approved retaining earnings for reinvestment. The company invests approximately 17% of revenue in R&D and has been funding significant manufacturing capacity expansion (capital expenditure peaked at approximately €230 million in FY2025 before being reduced to approximately €140 million for FY2026). The dividend-free policy reflects a growth reinvestment orientation.

Buybacks and dilution: Soitec operates a liquidity contract - a market-making arrangement common in French mid-cap companies where a financial intermediary uses a small pool of treasury shares to smooth daily trading volumes. This is not a buyback in the Anglo-Saxon sense; it does not structurally reduce share count. The company's share count has remained broadly stable at approximately 35.7 million shares. There has been no announced capital return program, no tender offer, and no buyback in the traditional sense over the last three years. Dilution from management options has been manageable, and the share count is essentially flat.

Verdict: Soitec is a Hoards Capital company. Its cash is directed at R&D and manufacturing investment, not returned to shareholders. This is the rational policy for a technology company with a monopoly in an exponentially growing market - but investors seeking current income or near-term capital return will not find it here.

Section 11: Insider Activities

Primary source: abcbourse.com, aggregating AMF (Autorité des Marchés Financiers) "Déclarations des dirigeants" filings for Soitec SA (ISIN FR0013227113). AMF MAR Art. 19 filings require PDMR notification within 3 business days.

Recent transactions (May 2025 to May 2026 - last 12 months):

Note: An earlier buy by Laurence Delpy (335 shares at approximately €60.10 in February 2025) falls marginally outside the trailing 12-month window but provides important context on price trajectory.

Reading the buys:

The November 2025 cluster is striking. Three insiders - the CEO, the Board Chair, and an independent board member - all made open-market purchases within 24 hours of the H1 FY2026 results announcement. That call contained the following bad news: a €41 million SmartSiC impairment, Barnabé's announced departure, a reduction in capital expenditure guidance, and revenue that had fallen roughly 30% year-on-year in the first half of FY2026. Despite that backdrop, all three insiders chose to buy.

The purchases are modest in absolute terms but significant in context. Pierre Barnabé was buying shares in a company he was leaving - his last day was March 31, 2026. That a departing CEO commits personal capital to the stock on the day of a bad results announcement is a meaningful conviction signal. Olivier Gégout (Board Chair) repeated a pattern of buying that had continued throughout 2024, consistently adding shares at progressively lower prices from over €90 in September 2024 to approximately €23 in November 2025. Laurence Delpy showed the same pattern, buying at €76.70 in October 2024, €60.10 in February 2025, and €27.19 in November 2025.

The cluster buy on November 20-21, 2025 - right at what appears to have been the stock's cyclical trough - is a bullish signal. Multiple insiders at different organizational levels buying simultaneously around a bad results announcement suggests genuine belief that the downturn was temporary, not structural.

Sells - the NSIG context: Outside the 12-month window (July 2024), NSIG Sunrise SARL (the entity controlled by Kai Seikku representing NSIG's board seat at Soitec) sold approximately 668,000 shares at prices around €110-113 per share, raising approximately €74 million in total. This occurred across May and July 2024. NSIG is Soitec's Chinese manufacturing partner, and this was a strategic divestment of their Soitec equity stake - not a traditional insider expressing a negative view on Soitec's fundamentals, but a corporate parent managing its investment portfolio. Kai Seikku subsequently left the Soitec board. NSIG's commercial relationship with Soitec (technology licensing, manufacturing partnership) remained intact and was extended in March 2026.

Net assessment: In the last 12 months, all insider activity has been buying - three open-market purchases by the CEO, Board Chair, and an independent director, all at multi-year price lows, clustering around the lowest-conviction reporting event in the company's recent history. No insider has sold in the trailing 12 months. The pattern is bullish, particularly given that the buying occurred when the headline numbers were at their worst. The cluster timing and the CEO's willingness to buy a stock he was about to leave are the strongest conviction signals. This is a bullish signal.

Section 12: Scenarios

Bull Case

The photonics thesis plays out faster than management guides. By 2027-2028, CPO adoption in AI switches goes from pilot deployments to mainstream architecture across NVIDIA, Broadcom, Intel, and Marvell product lines. Because each CPO module uses four times the Photonics-SOI area of a pluggable transceiver, Soitec's wafer shipments compound even faster than the number of data center ports being built. Tower Semiconductor's 5x capacity expansion is fully absorbed and Tower announces a further expansion. TSMC qualifies Soitec's photonics-SOI for its silicon photonics foundry offering, adding a second major photonics anchor customer.

Simultaneously, the RF-SOI inventory correction ends in H2 FY2026, and mobile communications revenue recovers toward structural demand levels. POI accelerates from ten production customers to twenty-plus as every major filter maker adopts it for sub-6GHz 5G applications - Skyworks' Sky5 deal proves to be the first of several multi-year supply agreements. FD-SOI design wins in Wi-Fi 7 and 5G mmWave translate into consistent volume production ramp at Samsung and GlobalFoundries.

The new CEO, Laurent Rémont, brings an RF background (Infineon's RF and Sensors division) that deepens Soitec's engagement with the RF front-end ecosystem while maintaining the photonics roadmap. The five product-line organizational structure delivers faster innovation cycles. SmartSiC finds a niche in data center UPS applications that justifies keeping the Bernin 4 asset partially active.

In this scenario, Soitec emerges from its FY2026 trough as a company with multiple growth vectors firing simultaneously and a monopoly position in the fastest-growing substrate segment on the planet.

Base Case

Photonics-SOI grows at management's guided 20-30% annually from its current base, driven by datacenter optical interconnect expansion and gradual CPO adoption. Tower Semiconductor's capacity expansion proceeds as planned and drives the majority of Soitec's photonics growth through FY2027. CPO commercialization begins to add volume in FY2028 rather than immediately.

Mobile communications recovers gradually through FY2027 as the RF-SOI inventory correction fully works through the system. The recovery is meaningful but does not return to prior-cycle peak volumes in the near term because structural demand growth (5G band additions, POI adoption) only partially offsets the completion of the one-time correction. POI continues its ramp at a measured pace, with the Skyworks deal providing revenue visibility.

SmartSiC remains a subscale business with manageable losses. Automotive Power-SOI stabilizes as vehicle electrification continues at a slower-than-hoped pace. FD-SOI grows steadily in edge AI, Wi-Fi 7, and select cybersecurity applications.

Laurent Rémont beds in the new organizational structure without major disruption. The NSIG partnership renewal provides stability in China. Free cash flow turns comfortably positive as capital expenditure stays disciplined and operating leverage returns with higher fab utilization.

Soitec becomes a company with a dominant photonics monopoly providing structural growth, a recovering mobile business providing cyclical upside, and an automotive business that is small and stable. The diversification strategy that management pursued over the last three years - getting four products each to roughly $100 million in annual revenue - delivers its intended resilience benefit.

Bear Case

The photonics thesis decelerates. AI infrastructure spending faces a multi-quarter pause as hyperscalers reassess their capital expenditure plans following uncertainty about the ROI of AI model deployment. Tower Semiconductor's expansion slows or its pre-reservations are renegotiated. CPO adoption is pushed back to 2029-2030 as technical challenges with co-packaged thermal management prove harder to solve than expected. Soitec's photonics revenue growth decelerates from 25-30% to high single digits.

Simultaneously, the RF-SOI inventory correction takes longer than expected - extending through FY2027. Chinese domestic RF chip production at Simgui and other Chinese suppliers reduces the addressable market for Soitec's direct RF-SOI shipments. Apple's supply chain shifts toward more Chinese semiconductor content, further reducing Western foundry RF-SOI volumes.

SmartSiC requires additional impairment as no automotive customer achieves production qualification and the data center UPS opportunity proves smaller than hoped. The carrying cost of Bernin 4 becomes a drag.

The new CEO, coming from outside, makes organizational decisions that alienate key engineers who were critical to Soitec's photonics process development. One or two key people leave. A competitor - potentially a Chinese company backed by state investment - makes unexpected progress toward qualifying photonics-grade SOI.

China geopolitical tension escalates in ways that force Soitec to terminate or significantly restrict the NSIG licensing arrangement, losing both royalty income and the managed access to China's domestic market.

In this scenario, Soitec's recovery from the FY2026 trough is slow and uneven. The photonics monopoly remains but grows more slowly than the market expected, and the mobile recovery is insufficient to offset the structural pressure in automotive. The company's operational excellence keeps it financially stable, but the growth story that drove the FY2026 re-rating disappoints on execution.

Sources:

• Soitec FY2025 Full Year Results - GlobeNewswire
• Soitec Q1 FY2026 Revenue Announcement - GlobeNewswire
• Soitec H1 FY2026 Results - Soitec.com press release
• Soitec Q3 FY2026 Revenue - GlobeNewswire
• Soitec Q3 FY2026 Earnings Summary - Quartr
• Soitec Q1 FY2026 Earnings Summary - Quartr
• Soitec Products Page
• Soitec Group Key Figures
• Soitec Investor Relations
• Soitec - Wikipedia
• Soitec H1 FY2026 Results - H1 FY2026 Results Full Year Results Page
• Soitec Skyworks POI Deal - GlobeNewswire
• Soitec and NSIG Framework Extension - GlobeNewswire
• Soitec Silicon Photonics CPO Contribution - Soitec.com
• Laurent Rémont CEO Appointment - Yahoo Finance
• This $2B Photonics Monopoly Down 75% Is Key To AI's Next Paradigm Shift - Asymmetrical Bets
• The Soitec Series Part 1 - Jason's Chips
• Insider Transactions - abcbourse.com (AMF filings aggregator)
• SOI Wafer Market Forecast - SemiconductorInsight
• SOI Wafers on the Move - SEMI
• Yole Group - Soitec Silicon Photonics and AI Data Centers
• SiC Market Growth 2025 - Digitimes
• Soitec Stock Overview - Stock Analysis