Taiwan Semiconductor Manufacturing Company Limited (TSM)

Deep Dive Research Report | May 12, 2026

Section 1: What the Company Does

Taiwan Semiconductor Manufacturing Company (TSMC) does one thing: it manufactures semiconductor chips for other companies' designs. It does not design chips. It does not sell products under its own brand. It makes chips, and it charges for that service. This sounds straightforward until you realize that the chips TSMC fabricates power every iPhone, every Nvidia GPU running AI training, every AMD processor, every Qualcomm modem, and most of the significant logic silicon produced in the world. TSMC's factories are where the designs of the world's most innovative technology companies become physical reality.

The pure-play foundry model - the concept that a company could exist solely to manufacture chips on behalf of designers who would never build their own factories - did not exist before TSMC. In 1987, Morris Chang, a 56-year-old veteran of Texas Instruments and General Instrument, founded TSMC in Hsinchu, Taiwan, with a mandate from the Taiwanese government to build a semiconductor industry for the nation. Chang recognized Taiwan had no competitive advantage in chip design or consumer electronics marketing, but it did have disciplined manufacturing talent, government support, and a willingness to industrialize. His insight was surgical: fabless chip designers could never emerge as an industry if the barrier to entry included building a billion-dollar factory. Remove the factory requirement, and design talent could proliferate everywhere.

TSMC opened in February 1987 with $220 million in seed capital - half from Taiwan's government through the National Development Fund (48% stake) and roughly 28% from Philips, which also licensed critical process technology. That initial capitalization would be dwarfed by what came after: by 2025, TSMC's annual revenue had reached roughly $122 billion, and its planned capital expenditure for 2026 alone stood at $52-56 billion - more than double its entire original capitalisation every single year.

The business model rests on a deliberately cultivated neutrality. TSMC commits to never competing with its customers. This is not merely a policy statement - it is the structural foundation of the company's existence. When Apple, Nvidia, and Qualcomm design a chip, they hand the blueprint to TSMC knowing that TSMC will not use the knowledge of their circuit designs to build competing products, will not favour one customer's capacity over another's in ways that could leak competitive advantage, and will treat each customer's intellectual property as sacrosanct. That trust, accumulated over 38 years, is itself a compounding asset.

What makes semiconductor manufacturing genuinely hard - and genuinely hard to replicate - is the combination of physics, chemistry, precision engineering, and institutional knowledge that must all work simultaneously. A modern chip is built by etching patterns of transistors onto silicon wafers through a process called photolithography. At the 3-nanometer node that TSMC was ramping in 2025, a transistor gate is roughly 3 nanometers wide - approximately 15 silicon atoms. To build millions of these gates reliably on a wafer the size of a dinner plate requires exposing the silicon to light through a mask at wavelengths of 13.5 nanometers (extreme ultraviolet light), depositing and etching dozens of distinct material layers with atomic-level precision, and doing all of this at yields - the percentage of functional chips per wafer - that make production economically viable.

TSMC currently uses 305 distinct process technologies to manufacture 12,682 different products for 534 customers. Each of those process technologies required years of development, equipment qualification, materials optimization, and yield improvement. When TSMC tells analysts that it takes two to three years to build a new fabrication facility and another one to two years to ramp to full yield, that timeline is not about construction - it is about the accumulation of process knowledge that cannot be transferred by hiring engineers or buying equipment.

A concrete example: when a customer like Nvidia designs an AI GPU for TSMC's N3 (3-nanometer) process, the design team co-develops the chip with TSMC's design enablement team, using TSMC's proprietary process design kits (PDKs) that specify exactly what the process can and cannot do. The chip goes through simulation, then mask-making at TSMC's mask shops, then a pilot production run (called a "tape-out"), then yield optimization, then volume manufacturing. From first tape-out to volume production can take 12-18 months. The PDK, the process know-how, the yield ramp experience - none of that transfers to a competitor even if a customer tried to switch. The Nvidia GB200 cannot be fabbed at Samsung without 12-18 months of re-qualification, assuming Samsung can even hit comparable yields at the relevant node.

"There are no shortcuts...it takes 2-3 years to build a new fab...another 1-2 years to ramp it up." - C.C. Wei, CEO, Q1 2026 Earnings Call

Section 2: Business Segments

TSMC reports its business through end-market platforms rather than distinct operating divisions - it is fundamentally a single-technology business serving multiple end markets from the same manufacturing infrastructure. However, the platform composition is so different in growth trajectory, technical requirements, and strategic importance that understanding each is essential.

High Performance Computing (HPC)

HPC is TSMC's largest and fastest-growing platform. In 2025, it generated 58% of total revenue and grew 48% year-over-year. By Q1 2026, it had grown to 61% of quarterly revenue. The customers in this segment are the most technically demanding and the most willing to pay for cutting-edge process technology.

HPC encompasses AI accelerators (principally Nvidia, AMD, and custom ASICs from Alphabet, Microsoft, Amazon, Meta, and Apple), CPUs (AMD, Apple's M-series processors), FPGAs (historically Intel/Altera and Xilinx/AMD), and networking chips. Every major AI training cluster being built globally - in data centers owned by the hyperscalers - relies on chips fabbed at TSMC. The H100 and H200 GPUs were N4/N4P (4-nanometer). The Blackwell architecture migrated to N3. The chips inside TSMC's most advanced fabs are predominantly bound for AI infrastructure.

What makes this segment structurally different from smartphones is its capital-intensity tolerance. A hyperscaler building a $10 billion AI cluster is not price-sensitive about whether a wafer costs 15% more at N3 versus N5. What they are sensitive about is yield (defective chips waste cluster deployment time), performance (more compute per watt translates directly into economics), and delivery certainty. TSMC's dominance in yield and performance at advanced nodes means HPC customers have no viable alternative at the cutting edge.

The shift from generative AI to what CEO C.C. Wei called "agentic AI" - AI systems that plan, reason, and take multi-step actions rather than just respond to prompts - is driving disproportionate compute demand growth. Agents run continuously, consume far more tokens per interaction, and require the kind of inference-optimized chips that are still manufactured exclusively at TSMC's most advanced nodes.

Smartphones

Smartphones accounted for 29% of TSMC's 2025 revenue and grew 11% year-over-year, recovering from an inventory correction cycle that dragged through 2023. The dominant customers are Apple (A-series and M-series chips, the modem following its acquisition of Intel's modem business), Qualcomm (Snapdragon application processors and modems for Android), and MediaTek (Dimensity SoCs for mid-range and premium Android).

The smartphone platform is characterized by predictable, large-volume ramps tied to annual product cycles. Apple's September iPhone launch creates a predictable demand spike at the leading edge - Apple historically books capacity at N3 beginning roughly 18 months ahead of volume. This predictability allows TSMC to plan capacity investments with high confidence.

Notably, the smartphone platform's share of TSMC revenue is declining structurally - not because smartphone demand is falling, but because HPC demand is growing faster. Nvidia's share of N3 wafer demand is expected to exceed Apple's by late 2027. This is not a risk for TSMC; it represents a customer mix improvement toward higher-margin, faster-growing applications.

Internet of Things (IoT)

IoT represented approximately 5% of 2025 revenue. This platform covers microcontrollers, sensors, connectivity chips, and the low-power, cost-sensitive chips embedded in everything from smart speakers to industrial equipment. IoT chips typically run on mature process nodes - 28nm, 40nm, 65nm - which are fully depreciated fabs with very high margins but limited growth.

The IoT segment's strategic importance is its breadth: 534 customers is a large number, and many of them are IoT companies placing orders across dozens of specialty process technologies. IoT also partially overlaps with what TSMC calls "specialty technologies" - including ultra-low-power, embedded flash, high-voltage, and radio-frequency processes.

Automotive

Automotive made up approximately 5% of 2025 revenue. This segment has been on a long-term growth trajectory as vehicles shift from primarily mechanical to primarily electronic systems. The average content of semiconductors per vehicle has grown dramatically, and electric vehicles require substantially more chips than internal combustion engines.

Automotive chips are unusual because they require qualification to AECQ standards (automotive electronics reliability specifications), which is time-consuming and expensive. Once a chip is qualified for use in a specific vehicle platform - typically a 5-7 year automotive program - switching suppliers is extraordinarily difficult. This creates substantial switching costs that compound TSMC's structural position.

The automotive segment also involves relatively lower process nodes (28nm to 7nm for most applications, with some advanced driver assistance systems pushing to 5nm) but with very long product lifecycles, which suits TSMC's mature node fabs.

Digital Consumer Electronics and Other

The remaining revenue covers consumer devices such as game consoles, TVs, cameras, and wearables. This is a cyclical, price-competitive segment where TSMC's value proposition is less about cutting-edge nodes and more about scale and specialty capabilities.

Segment Comparison Table

Section 3: Products and Business Detail

The Full Process Technology Catalogue

TSMC's "products" are process technologies - each one a recipe for building transistors and interconnects at a specific scale using specific materials and techniques. TSMC maintains 305 distinct process technologies spanning nodes from cutting-edge 2nm to legacy 0.35-micron processes that remain in production for legacy industrial and automotive applications.

Advanced Nodes (7nm and Below)

Advanced nodes generated 74-77% of wafer revenue in 2025 and 2026. The full family:

• N7 / N7+ (7nm): Introduced 2018. The node that first brought extreme ultraviolet (EUV) lithography to production. Still generating 13-14% of wafer revenue in 2025-26 as older chip designs remain in production and some customers use it as a cost-optimized alternative to N5.

• N5 / N5P (5nm): Introduced 2020. Apple's first 5nm chip was the A14 in 2020. N5 and its performance-enhanced variant N5P ran at 34-37% of wafer revenue through 2025-early 2026. Capacity described as "very tight" for "a couple of years" in the Q2 2025 concall.

• N4 / N4P / N4X: These are enhanced variants of N5 that deliver better performance and density on the same basic process platform. The first Arizona fab is producing N4 (Apple silicon for Mac, some iPhone chips). N4X is a variant optimized for extreme performance HPC chips.

• N3 / N3E / N3P / N3X: Introduced 2022. TSMC's FinFET (fin field-effect transistor) process at 3nm. N3E is the high-volume, yield-optimized variant that most customers use. N3P adds performance enhancement; N3X is optimized for extreme compute. In Q4 2025, 3nm contributed 28% of wafer revenue. In Q1 2026, it contributed 25% (mix shifted as N2 began ramping). N3 supply is expected to remain "very tight" through at least 2026 as AI demand absorbs all available capacity. Arizona's second fab and TSMC's new Taiwan Tainan fab will expand N3 capacity through 2027.

• N2 / N2P / N2X (2nm): The most significant architectural transition in a decade. N2 marks TSMC's shift from FinFET transistors to Gate-All-Around (GAA) nanosheet transistors. In a FinFET, the gate wraps around three sides of the channel. In GAA nanosheet, the gate wraps fully around a thin sheet of silicon - improving electrostatic control, reducing leakage, and enabling further power/performance improvement. N2 entered high-volume manufacturing in Q4 2025 at Hsinchu and Kaohsiung. N2P (enhanced performance) enters volume production H2 2026. As of Q1 2026, N2 was ramping with strong demand from both smartphone and HPC/AI customers, with 20+ tape-outs received and 70+ in the pipeline.

A-Series (Angstrom Nodes)

• A16 (approximately 1.6nm): Combines N2's GAA nanosheet transistors with a Backside Power Delivery Network (BSPDN). In conventional chips, power and signal are routed on the same interconnect layers, competing for area. BSPDN routes power delivery to the backside of the wafer, freeing the front side entirely for signal routing. This enables approximately 15% power savings, 25% cell height reduction, and improved clock distribution. A16 was originally guided for H2 2026 in multiple prior calls; the April 2026 TSMC Technology Symposium confirmed a slip to 2027. A16 is optimized specifically for high-performance data center applications.

• A14 (approximately 1.4nm): Development is "ahead of schedule" per the Q1 2026 concall, with volume production targeted for 2028. Expected to deliver "10-15% speed improvement or 25-30% power improvement" versus N2.

• A13 / A12: Both announced at the April 2026 Technology Symposium for 2029 production.

Specialty Technologies

TSMC's specialty portfolio covers: ultra-low-power processes (N22ULP, N16FFC+), embedded Flash for automotive microcontrollers (eFlash at 40nm to 12nm), High Voltage (for power management, displays), Radio-Frequency CMOS (for 5G/WiFi), Silicon Photonics, and Image Sensor processes (BSI CMOS). These are older, largely depreciated nodes that serve markets where feature size is less critical than specific electrical characteristics. They provide steady, margin-accretive revenue.

Advanced Packaging - 3DFabric

TSMC's 3DFabric portfolio is arguably its fastest-growing non-wafer business and a critical enabler of AI infrastructure. As transistor scaling slows, packaging - stacking multiple dies together to act as a single chip - has become the new frontier of performance improvement.

CoWoS (Chip-on-Wafer-on-Substrate): The dominant packaging technology for AI accelerators. Nvidia's GPUs use CoWoS-S (silicon interposer-based) to integrate the GPU die alongside up to 12 High Bandwidth Memory (HBM) stacks on a single substrate. In 2025, CoWoS revenue reached $9.6 billion, growing 2.5x versus InFO revenue. TSMC is manufacturing CoWoS packages up to 5.5 reticle sizes (approximately 4,800mm²) in 2026, scaling to 9.5 reticle sizes in 2027 and 14 reticle sizes in 2028. Each generation of expansion enables more dies and HBM stacks per package, directly supporting higher-performance AI cluster interconnects.

SoIC (System on Integrated Chips): TSMC's face-to-face die stacking technology. SoIC-X uses direct copper-to-copper hybrid bonding at pitches as fine as 9 micrometers. It allows compute dies to be stacked with extraordinary bandwidth density - far exceeding conventional packaging. SoIC capacity is growing by over 90% annually. The "N2-on-N2 SoIC" is in production; "A14-to-A14 SoIC" is targeted for 2029, promising 1.8x the inter-die I/O density of the current generation.

InFO (Integrated Fan-Out): A fan-out wafer-level packaging technology primarily used for Apple's A-series chips. InFO enables thinner form factors and better thermal performance than conventional flip-chip packaging, which matters for mobile devices.

Manufacturing Facilities

TSMC's global manufacturing footprint spans four countries, with Taiwan remaining the overwhelmingly dominant production base:

Taiwan:

• Hsinchu: Fabs 2, 3, 5, 6, 8, 12, 14, 15 - spanning 0.35-micron to 2nm
• Taichung: Fab 15 (specialty, mature nodes)
• Tainan: Fab 18 (Apple's 5nm, 3nm center), new N3 fab in construction (volume production H1 2027)
• Kaohsiung: Advanced fab (N2 in production as of Q4 2025)
• In planning: 11 wafer fabs, 4 advanced packaging facilities in Taiwan over coming years

Arizona, USA:

• Fab 21 Phase 1: 4nm (N4) in production, yields reportedly at ~92%, comparable to Taiwan equivalents
• Fab 21 Phase 2: 3nm (N3), construction complete, volume production H2 2027 (pulled forward from 2028)
• Fab 21 Phase 3: Under construction, targeting N2 and A16
• Fab 21 Phase 4: Permit applications filed
• Total committed U.S. investment: $165 billion across 6 fabs, 2 packaging facilities, and an R&D center - described as one of the largest foreign direct investments in U.S. history
• TSMC describes Arizona as targeting a "giga fab cluster" - a scale comparable to Taiwan's Hsinchu science park

Japan:

• Fab JASM Kumamoto (Fab 1): Specialty node fab (22nm/28nm) in volume production since late 2024
• JASM Kumamoto (Fab 2): Construction starting in 2025, targeting N3 by 2028 - a significant step-up from Fab 1's specialty focus

Germany (Dresden):

• European Semiconductor Manufacturing Company (ESMC) joint venture with NXP, Infineon, and Bosch
• Specialty nodes (12nm/16nm) for automotive and industrial applications
• Construction under way, supported by European Commission CHIPS Act funding and German government grants
• Production targeted for late 2027

Revenue Geography

North America generated 75% of TSMC's 2025 net revenue - reflecting the concentration of leading-edge chip design activity in the United States. This geographic skew is actually a design-location statistic, not a consumption statistic: the chips may be designed in California, fabbed in Taiwan, and assembled in Vietnam before landing in devices sold globally.

Section 4: Customers

Who Buys and Why

TSMC's customers are semiconductor design companies - both "fabless" companies (companies that design chips but own no manufacturing facilities) and "integrated device manufacturers" (IDMs) that have their own fabs but outsource overflow or specific nodes to TSMC. The buying decision is made by engineering and procurement teams at the chip design companies, and the criteria are brutally specific: process performance (transistor speed, power consumption, density), yield reliability, capacity availability, design support quality (PDK completeness, physical design rules), and total cost.

Nvidia - the largest single customer as of 2025, generating approximately 22% of TSMC revenue. Nvidia's AI GPU business depends on TSMC N4/N3 for training GPUs (H100, H200, B100 Blackwell) and CoWoS packaging for the HBM integration that makes AI clusters functional. Nvidia has no foundry alternative for its leading-edge products - Samsung's comparable nodes lag in yield and density, and Intel Foundry is not yet qualified for Nvidia's requirements. The switching cost is measured in years of qualification work and production yield risk.

Apple - approximately 18-20% of revenue, second after Nvidia. Apple's annual A-series iPhone chip, M-series Mac chip, and now its in-house modem are all TSMC customers, running on N3, N4, and N5. Apple has historically been TSMC's "anchor tenant" - the large-volume, leading-edge customer that funds a significant portion of each new node's yield learning curve. Apple's own silicon team co-develops new process features with TSMC years before other customers can access them. However, early 2026 reports indicate Apple is exploring Intel's 18A process for base-model M-series chips as a risk hedge against Taiwan concentration.

Broadcom and Marvell - ASIC design houses that build custom AI chips for hyperscalers (Alphabet's TPU, Meta's MTIA, Amazon's Trainium/Inferentia are all fabbed by TSMC through these partners). Combined, hyperscaler ASICs through TSMC represent a fast-growing revenue stream that reduces any single customer's concentration.

AMD - CPUs (Ryzen, EPYC) and GPUs (Radeon) all manufactured at TSMC, primarily on N5 and N3. AMD moved its production from GlobalFoundries to TSMC in 2017 and has not looked back.

Qualcomm - Snapdragon application processors and 5G modems, primarily on N4 and N5.

MediaTek - Dimensity SoCs for Android smartphones, primarily on N4 and N5. One of TSMC's top 5 customers by volume.

Intel - now a customer as well as a competitor. Intel's 18A process for its own CPUs competes with TSMC; simultaneously, Intel outsources some products to TSMC's N3 and N5.

The top 10 customers represented approximately 76% of 2024 revenue, and the top 5 (Nvidia, Apple, AMD, Broadcom, Qualcomm) approximately 65-70% of 2025 revenue.

Switching Costs

The switching cost for a customer at the leading edge is enormous. A chip designed for TSMC's N3 process must be re-designed and re-validated for Samsung's 3GAE (3nm GAA) process - the transistor physics, design rules, PDK parameters, and parasitic characteristics are all different. This involves 12-18 months of engineering work, new mask sets (which cost millions of dollars per chip), and production risk. For a company like Nvidia, whose roadmap is committed quarters ahead and whose customers have integration timelines tied to their systems, re-qualification at a new foundry is simply not possible within any planning horizon that matters. TSMC's customers are sticky in the extreme.

For mature nodes, switching costs are lower - a 40nm automotive microcontroller could potentially move from TSMC to UMC or GlobalFoundries with less disruption. This is why TSMC faces more competitive pressure on specialty and mature nodes than on advanced logic.

Contract Structure

TSMC uses a combination of long-term supply agreements (particularly with major customers who need capacity assurance) and spot/shorter-term purchase orders. During periods of tight supply (2020-2022 shortage, current AI-driven tightness), customers commit capacity years ahead with non-cancellable purchase commitments. During Q2 2025, C.C. Wei noted that TSMC's planning horizon with customers had extended to 2-3 years of engagement visibility, providing unusually deep demand confidence. This forward booking also means TSMC can commit to CapEx with high conviction.

Section 5: Competitive Landscape

The Foundry Hierarchy

The global semiconductor foundry market generated approximately $169.5 billion in revenue in 2025, growing 26.3% year-over-year. TSMC commands approximately 70% of this market - a share that, far from being a temporary aberration, has been widening for a decade.

Samsung Foundry - the number two player, but at a distant 7% market share. Samsung has the theoretical advantages of scale (it is also the world's largest memory maker), a complete in-house semiconductor ecosystem, and substantial government support from Seoul. Its foundry business, however, has struggled chronically with yield at advanced nodes. Samsung's 4nm (SF4) process had well-documented yield problems that cost it Qualcomm's Snapdragon 8 Gen 2 volume production (which Qualcomm shifted to TSMC). Samsung's 3nm GAA node (SF3) was supposed to be a competitive leap but has faced customer adoption challenges. As of 2025-26, Samsung's foundry market share has continued to erode rather than recover. Its primary strength is in producing DRAM logic dies (for HBM) and some image sensors - not in competing for leading-edge logic.

Intel Foundry Services (IFS) - Intel's attempt to become a third leading-edge foundry has so far not appeared in the top 10 foundry rankings by revenue. Intel 18A, featuring both GAA (RibbonFET) and BSPDN (PowerVia), is technically competitive on paper and actually first to market with both features. Several companies including Amazon and Microsoft have publicly taped out test chips on 18A. However, Intel is manufacturing chips primarily for its own CPU business (Intel 3, Intel 20A) and has not yet demonstrated the manufacturing volume, yield consistency, or customer base needed to challenge TSMC at scale. The timeline from "tape-out" to "TSMC alternative" spans multiple years and billions in unproven investment.

SMIC - China's largest foundry, at approximately 5% global share. SMIC is technically capable at mature nodes (28nm volume production) and has reportedly made limited progress at 7nm (using deep-UV multi-patterning, not EUV). However, SMIC is subject to US export controls that restrict its access to EUV lithography equipment and advanced chip-making tools. Without EUV, SMIC cannot advance to N5 or below using conventional approaches. SMIC primarily serves domestic Chinese customers and Chinese government-mandated technology localization programs.

UMC (United Microelectronics Corporation) - Taiwan-based, approximately 4.4% share. UMC focuses primarily on mature and specialty nodes (28nm to 65nm) and does not compete with TSMC at advanced nodes. A reasonable competitive alternative for IoT and automotive chips.

GlobalFoundries - US/Abu Dhabi-based, approximately 3.9% share. GF exited the leading-edge race in 2018, abandoning 7nm development to focus on specialty processes (FD-SOI, RF, embedded flash). A strong competitor for specialty applications but not a threat at advanced logic.

Rapidus - Japan's new national foundry project, targeting 2nm by 2027 with BSPDN. IBM technology licensing and IMEC support. The timeline is ambitious - the company is building from scratch with no production history. The industry is skeptical about the 2027 timeline, and even if achieved, ramping yield and customer qualification would require years beyond first silicon.

Why TSMC Wins

TSMC's competitive position rests on four mutually reinforcing advantages that have compounded over 38 years:

1. Yield leadership: Making a chip at TSMC's N3 with 80% yield versus a competitor's 60% yield is not a 20-percentage-point difference in output - it is the difference between a profitable business and an unviable one for the customer. Yield is the accumulated product of thousands of process optimizations, equipment mastery, contamination control, and design rule refinements. It cannot be acquired quickly.

2. Technology cadence: TSMC has delivered on its node roadmap with remarkable consistency. N2 entering HVM on schedule in Q4 2025 validated the transition to GAA. A14 development ahead of schedule. Customers who plan product roadmaps 2-3 years ahead cannot afford to bet on a foundry whose process technology timeline is uncertain.

3. Scale of R&D reinvestment: With 70-80% of a $52-56 billion CapEx budget going to advanced processes, TSMC is reinvesting at a pace that no competitor can match. Samsung's total foundry CapEx is a fraction of TSMC's. Intel Foundry is investing heavily but its primary obligation is to Intel's own product business.

4. Customer network and design ecosystem: 534 customers and 305 process technologies means TSMC has the richest process design kit ecosystem, the most extensive customer reference designs, the deepest pool of design engineers experienced with its processes, and the broadest IP library. Starting a new foundry means starting with zero design wins, zero ecosystem, and zero yield history - a self-reinforcing disadvantage.

Barriers to Entry

The barriers to entry in leading-edge semiconductor manufacturing are among the highest in any industry:

• Capital: A leading-edge fab costs $15-20 billion. Six fabs cost $90-120 billion. TSMC spent $101 billion in CapEx over the three years ending 2025 alone.
• Talent: TSMC employs over 75,000 people in Taiwan alone, including thousands of process engineers who have spent careers developing specific node expertise. This knowledge walks out the door if TSMC falters, but it took decades to accumulate.
• Equipment: Extreme ultraviolet lithography machines from ASML cost approximately $200 million each, take two years to order and deliver, and require dedicated customer engineering teams to operate. TSMC is ASML's largest customer, buying approximately 20% of ASML's output. New entrants go to the back of the equipment queue.
• Customer relationships and IP: PDKs developed jointly with Apple or Nvidia over years are not transferable. Process qualification data accumulated over billions of wafers cannot be replicated.
• Time: Two to three years to build a fab plus one to two years to ramp yield. Even well-funded nation-states (US CHIPS Act, European CHIPS Act, Japan government support) are finding the timeline for new capacity is measured in half-decades.

Section 6: Industry

What Drives Demand

The semiconductor foundry industry's demand is driven by the insatiable need for computing capability across every layer of the economy. The current cycle is dominated by one factor above all others: artificial intelligence infrastructure.

AI training and inference workloads require chips that push the absolute frontier of transistor density, power efficiency, and interconnect bandwidth. Language models have grown from billions to trillions of parameters. Inference clusters serving AI applications run continuously at scale. Every percentage point of transistor density improvement translates directly to more tokens per second per watt, which translates to data center economics. The shift from generative to agentic AI, which C.C. Wei highlighted explicitly in the Q1 2026 call, compounds this: agents run background processes continuously rather than responding to discrete queries, requiring yet more persistent compute.

Beyond AI, the electrification of vehicles, the build-out of 5G infrastructure, and the general digitization of industrial processes all represent long-cycle semiconductor demand drivers that are structural rather than cyclical.

Industry Size

The leading semiconductor foundry group revenues reached approximately $169.5 billion in 2025, up 26.3%. TrendForce projects global foundry revenue reaching $218.8 billion in 2026, implying 29% growth. Longer-term, the broader semiconductor industry could reach $1.6 trillion by 2030 per McKinsey's base case, from $775 billion in 2024. Advanced node capacity (7nm and below) is projected to grow approximately 69% from 2024 to 2028, representing a CAGR of about 14%.

TSMC's Position in the Supply Chain

TSMC sits at the most capital-intensive and technically complex point in the electronics supply chain - the inflection point between design (intellectual) and manufacturing (physical). Upstream of TSMC are equipment makers (ASML, Applied Materials, Tokyo Electron, Lam Research), chemical and materials suppliers (Shin-Etsu for silicon wafers, Air Liquide and Air Products for process gases), and mask makers. Downstream are chip designers (Nvidia, Apple, Qualcomm), package assembly and test houses (ASE, Amkor), and eventually system integrators. TSMC is the unavoidable chokepoint - every chip that needs advanced process manufacturing must flow through it.

Regulation and Geopolitics

The semiconductor industry has become one of the most geopolitically sensitive sectors in the global economy. US export controls introduced under both the Biden and Trump administrations restrict the export of advanced semiconductor equipment and chips to China, and have specifically targeted TSMC's ability to manufacture advanced chips for Chinese customers. TSMC complied with these restrictions and reduced its China revenue exposure. The US CHIPS and Science Act ($52 billion in US subsidies) was explicitly designed to incentivize TSMC, Intel, and Samsung to build advanced fabs in the United States - and TSMC's $165 billion Arizona commitment is the direct result.

Taiwan's geopolitical status - the subject of cross-strait tensions with China - creates a baseline tail risk for the entire industry. The concentration of world-leading semiconductor capacity in Taiwan is described by strategists as the "silicon shield" (the economic interdependence that makes conflict self-defeating) and the "silicon nightmare" (the supply chain catastrophe that would result from any disruption). TSMC's overseas expansion directly addresses this by distributing advanced manufacturing to the US, Japan, and Europe - though Taiwan will remain the majority of production capacity for the foreseeable future.

Cyclicality

The semiconductor industry is cyclical, but the foundry business - particularly at the leading edge - has been increasingly buffered from demand cyclicality by structural growth in AI. The 2022-2023 inventory correction primarily impacted mature nodes and consumer-facing chips (smartphones, PCs) rather than advanced HPC nodes. During Q3 2025, management noted that "non-AI chip markets are still in recovery mode" while AI demand continued to accelerate - a bifurcation that illustrates the two-speed nature of the industry.

Historical downturns have been amplified at TSMC's level by the order visibility problem: customers over-order during shortages and cancel during corrections. The multi-year engagement windows that C.C. Wei cited - customers booking capacity 2-3 years ahead - represent a structural improvement in demand visibility compared to prior cycles.

Section 7: Growth Triggers

All triggers below are sourced directly from the four earnings calls used in this report.

• N2 fast ramp in 2026: "We expect a faster ramp in 2026, fueled by both smartphone and HPC AI applications." N2 entered HVM in Q4 2025 with good yield. TSMC has already received 20+ customer tape-outs with 70+ in the pipeline. (Q4 2025 concall, January 15, 2026; confirmed Q1 2026 concall, April 16, 2026)

"N2 customers are happy with the performance, power and yield, and we are working hard to expand N2 capacity." - C.C. Wei, Q1 2026 Earnings Call

• Arizona Fab 2 (N3) entering volume production H2 2027: Second Arizona fab construction is complete and pulled forward from original 2028 schedule due to customer demand. This adds a significant block of N3 capacity outside Taiwan. (Q4 2025, Q1 2026)

• Agentic AI driving step-change in compute demand: CEO explicitly described the transition from "generative AI and query mode to agentic AI and command and action mode" as driving a step increase in token consumption and therefore silicon demand. Cloud service providers signaled "very strong" positive outlooks. (Q1 2026 concall, April 16, 2026)

"The AI demand continues to be extremely robust. And the [shift to] agentic AI is driving the need for more and more computation." - C.C. Wei, Q1 2026 Earnings Call

• N3 capacity tightening further on AI demand: N3 node utilization expected to exceed 100% in H2 2026 per industry reports; TSMC confirming supply will remain "very tight" through 2027. Three new fabs adding N3 capacity (Tainan Taiwan H1 2027, Arizona H2 2027, Kumamoto Japan 2028). (Q3 2025, Q4 2025, Q1 2026)

• N3 reaching corporate average gross margins in H2 2026: "N3 is finally going to match the overall corporate average margins in 2026" (per MBI's read of Q1 2026). This is significant because N3's yield improvement eliminates a current margin drag and lifts overall profitability. (Q1 2026 concall, April 16, 2026)

• A14 development ahead of schedule, volume production 2028: A14 promises "10-15% speed improvement or 25-30% power improvement" versus N2. Management called development "ahead of schedule." New announcement of A13/A12 for 2029 also signals runway beyond. (Q1 2026 concall, April 16, 2026)

• Sovereign AI demand as new growth driver: Emerging "sovereign AI" investments - national governments building their own AI infrastructure - flagged as a new structural demand source supplementing hyperscaler spend. (Q2 2025 concall, July 17, 2025)

• AI accelerator revenue CAGR of mid-to-high 50s% (2024-2029): Management guided a multi-year CAGR for AI accelerator-specific revenue that implies continued doubling of this platform roughly every 18 months. (Q4 2025 concall, January 15, 2026)

"We believe the AI is real. Not only real, is starting to grow into our daily life." - C.C. Wei, Q4 2025 Earnings Call

• 25% overall revenue CAGR (2024-2029): Five-year growth framework cited explicitly. (Q4 2025 concall, January 15, 2026)

• CoWoS capacity doubling through 2026: TSMC doubling CoWoS packaging capacity to break the supply bottleneck for AI accelerators. Interposer sizes scaling from 5.5x reticle (2026) to 9.5x (2027). Each generation enables more powerful AI packages. (Q3 2025, Q4 2025)

• Japan Kumamoto second fab 3nm, volume production 2028: A step up from the first Japan fab's specialty nodes - signals Japan becoming a leading-edge site. (Q1 2026 concall, April 16, 2026)

Section 8: Key Risks

1. Taiwan Geopolitical Risk

This is TSMC's most discussed risk and the one it is actively spending $165 billion to mitigate. If China were to attempt military unification with Taiwan - or even to impose a naval blockade or conduct a sustained cyber campaign against TSMC's operations - the global supply of advanced semiconductor chips would be severely disrupted within months. Over 80% of TSMC's advanced capacity remains in Taiwan. The Arizona, Japan, and Germany expansions are meaningful but will represent at most 15-20% of advanced capacity by 2028.

The mechanism matters: a kinetic conflict that physically destroys TSMC's fabs would set AI development back years and crater the global technology industry. A coercive campaign short of direct military action could force TSMC to operate under Chinese political constraints. The "silicon shield" theory - that China would never act because it would destroy its own semiconductor supply chain - assumes China's leadership makes economically rational decisions. The risk probability is genuinely hard to estimate, but the impact is catastrophic.

Management does not discuss this risk directly in earnings calls - it is addressed at the board level and through the geographic diversification strategy. The Q1 2026 call's mention of "Middle East geopolitical uncertainty" as a materials supply risk is the only geopolitical discussion in recent calls, which understates the Taiwan-specific exposure.

2. Customer Concentration

The top 5 customers represent 65-70% of revenue. Nvidia alone is approximately 22%. While Nvidia's AI roadmap currently makes it an effectively captive TSMC customer, any scenario that reduces Nvidia's demand - an AI investment cycle correction, a breakthrough in inference efficiency that dramatically reduces hardware requirements, or regulatory restrictions on AI hardware sales - would have outsized impact on TSMC. During prior semiconductor cycles, even TSMC's largest customers have reduced orders materially.

Apple, the second-largest customer, is actively exploring Intel's 18A process for some product lines. If Apple successfully qualifies Intel 18A (or any other foundry) for leading-edge production, it would not only reduce TSMC concentration but signal the ecosystem that alternatives are viable - a second-order risk.

3. The Capital Intensity Trap

TSMC's guidance of $52-56 billion in CapEx for 2026 alone is enormous. The risk is not that the investment is wrong - it is that demand shifts before the capacity is paid for. Semiconductor equipment is largely non-refundable: once ASML EUV machines are delivered and installed, the cost is sunk. If AI investment were to slow materially in 2027-2028 while TSMC is ramping N2 and bringing Arizona fabs online, the combination of high depreciation (increasing "high-teens %" per year) and lower utilization would compress margins significantly. Management acknowledged this dynamic by noting that depreciation growth will accelerate in the 2026-2027 window.

C.C. Wei addressed this concern directly when analyst Gokul Hariharan raised AI bubble concerns in Q4 2025, citing direct visibility into customer financial capacity and order commitments. But the pattern of technology investment cycles - enthusiasm followed by digestion - is consistent, even if the specific trigger is hard to predict.

4. Overseas Fab Execution Risk and Margin Dilution

Building leading-edge fabs outside Taiwan has proven harder than originally expected. Early Arizona yields were below Taiwan benchmarks before improving. Labor productivity differences, supply chain proximity issues, and cultural management challenges have all contributed to the higher cost structure of overseas fabs. Management quantified this: overseas fab dilution is running at 2-3% on gross margin today and expected to widen to 3-4% as more overseas capacity comes online.

This is a multi-year structural headwind that management is actively managing but cannot eliminate quickly. Building a fab cluster in Arizona that matches the efficiency of Hsinchu - a place that has been doing this for 40 years - is a 10-15 year project, not a 3-year one.

5. Technology Execution Risk at GAA Transition

The shift from FinFET to Gate-All-Around nanosheet transistors at N2 is the most significant architectural transistor change in over a decade. While N2 has entered volume production with "good yield," the full ramp through 2026 and 2027 will test whether TSMC can execute consistently across high volumes. Historically, every major node transition has involved early yield challenges. Samsung's 3nm GAA (SF3) suffered from exactly this - poor yield that repelled customers. If N2 ramp encounters similar challenges at volume, it would delay revenue recognition and disappoint demand-side customers who have product commitments.

A16's slip from H2 2026 to 2027 (confirmed at the April 2026 Technology Symposium) suggests that BSPDN integration adds genuine complexity. A16 is not yet in customer hands, and its production ramp carries execution risk beyond N2.

6. US Export Controls and Tariff Policy

The US government has incrementally tightened restrictions on semiconductor exports to China. TSMC has complied and reduced its China-destined advanced chip revenue. Future restrictions - potentially including restrictions on TSMC serving Chinese fabless designers even on mature nodes - could reduce revenue from a market segment. Additionally, the Q3 2025 call explicitly noted tariff-related uncertainty for "consumer related and price sensitive end market segment." A sharp escalation in trade tensions could slow smartphone and consumer electronics demand globally.

7. Foreign Exchange Risk

TSMC's revenue is predominantly in US dollars (North America is 75% of revenue) while its cost base is predominantly in New Taiwan Dollars. A stronger TWD against USD reduces the TWD-denominated value of TSMC's earnings. The Q2 2025 call cited "unfavorable exchange rates" as a gross margin headwind. Management acknowledged that when FX is unfavorable, they "focus on the fundamentals of the business and lean on the other five factors" (technology, efficiency, capacity, service, and pricing) to compensate.

Section 9: Walk the Talk

The four concalls used for this analysis are:

• Q2 2025 (July 17, 2025)
• Q3 2025 (October 17, 2025)
• Q4 2025 (January 15, 2026)
• Q1 2026 (April 16, 2026)

The most recent concall (Q1 2026) was held 26 days ago. It falls within the required 90-day window.

TSMC's management - primarily CEO C.C. Wei and CFO Wendell Huang (with former CFO Jen-Chau Huang overlapping in mid-2025) - have a strong track record of delivering on or above guidance across these four calls.

Starting with the Q2 2025 call, TSMC had just reported revenue of $30.1 billion on a guidance range that was met. Management guided Q3 2025 revenue at $31.8-33.0 billion and gross margin at 55.5-57.5%. The tone was measured: full-year 2025 growth "around 30%," N2 on track for H2 2025 volume production, Arizona expansion proceeding, and gross margin targets maintained at "53% and higher" for the long term.

Q3 2025 arrived, and TSMC delivered revenue of $33.1 billion - exceeding the top of the $31.8-33.0 billion guidance range. Gross margin came in at 59.5%, beating the guided top end of 57.5% by a full 200 basis points. This is not a minor beat - 200 basis points on a company of this size represents a substantial positive surprise on profitability. Management acknowledged that AI demand had become "more stronger than we thought 3 months ago" - an unusually direct concession that they had underestimated demand velocity.

"AI demand actually continue to be very strong, it's more -- more stronger than we thought 3 months ago." - C.C. Wei, Q3 2025 Earnings Call

From Q3 2025, TSMC guided Q4 at $32.2-33.4 billion revenue and 59-61% gross margin. Actual Q4 2025 results came in at $33.7 billion revenue - again above the top of the guidance range - and gross margin of 62.3%, exceeding the 61% ceiling by 130 basis points. This represents a pattern: management's revenue guidance has been systematically beaten by hitting the top or exceeding the top of the range in consecutive quarters.

On the N2 technology promise: in Q2 2025, management committed to N2 volume production "on track for 2025." In Q3 2025, they confirmed N2 production "on track for volume production in Q4 2025." In Q4 2025, they confirmed N2 "successfully entered high-volume manufacturing in Q4 2025 at Hsinchu and Kaohsiung, with good yield." This is a clean kept promise - announced, tracked through two interim calls, and delivered on schedule.

The gross margin long-term target also evolved in a positive direction: in Q2 2025, the long-term target was "53% and higher." By Q4 2025, management raised this to "56% and higher." By Q1 2026, actual gross margin was 66.2% - far above the target - and the "56% and higher through cycle" language remains the conservative floor. When management says "56% and higher," they appear to mean it as a floor, not a ceiling.

From Q4 2025, management guided Q1 2026 revenue at $34.6-35.8 billion and gross margin at 63-65%. Q1 2026 delivered revenue of $35.9 billion (above top of range) and gross margin of 66.2% (above top of range by 120 basis points). This is now four consecutive quarters of beating the top of revenue guidance. The gross margin outperformance is attributable partly to FX tailwinds, partly to N3 yield maturity, and partly to the favorable mix shift toward HPC and AI chips.

One commitment that is under monitoring rather than confirmed delivered: the A16 timeline. Q2 and Q3 2025 calls referenced A16 volume production in "H2 2026." The April 2026 TSMC Technology Symposium (after the Q1 2026 call) confirmed a slip to 2027. This was not flagged as a risk in any of the four calls - the Q1 2026 call cited A16 for "H2 2026" without signaling the slip that was later confirmed at the symposium. This is the most notable instance of guidance not being delivered, though the delay is one year rather than a cancellation.

Assessment: TSMC management's operational guidance - particularly revenue and gross margin - has been conservative and consistently beaten. The N2 production milestone was delivered exactly as promised across three concalls. The long-term gross margin target has been raised. The one delivery miss - A16 timing slip - was not signaled in advance and represents a minor credibility gap. Overall, this is management that understates near-term performance and executes on technology roadmap milestones. Investors should treat their guidance as floors, not ceilings.

Section 10: Shareholder Friendliness Index

TSMC pays a quarterly cash dividend that has grown meaningfully over the last three years. On an ADR basis (each ADR represents 5 common shares), the annual dividend moved from approximately $1.44-1.53 per ADR in 2022, dipped slightly to $1.39-1.45 per ADR in 2023 (reflecting the inventory correction-driven earnings pause), recovered to $1.53-1.83 per ADR in 2024, and accelerated sharply to approximately $2.64 per ADR on an annualized basis by late 2025-early 2026, representing approximately 36% dividend growth year-over-year. At the Q4 2025 call, TSMC committed to a minimum cash dividend of TWD 23 per common share in 2026, up from TWD 18 in 2025 - a 28% increase in TWD terms. The company generated approximately TWD 1 trillion in free cash flow in 2025, and its dividend policy explicitly targets "sustainable and steadily increasing cash dividends per share."

TSMC does not conduct share buybacks in any meaningful volume. Its shares outstanding have remained essentially stable with mild dilution from employee stock plans. The capital return strategy is dividends only - a deliberate choice given the scale of CapEx requirements. With $52-56 billion needed in 2026 CapEx alone, the company deploys excess cash flow into capacity investment rather than capital return. The lack of buybacks is not a shareholder hostility signal but a reflection of the genuine capital intensity of being the world's most critical semiconductor manufacturer during an AI infrastructure supercycle.

Verdict: Returns Capital via growing dividends only - buybacks absent because CapEx requirements leave little room, but dividend growth is consistent and above-inflation.

Section 11: Insider Activities

Primary source: SEC Form 4 filings via EDGAR (TSM NYSE ADR listing); Taiwan listings would additionally report through MOPS (mops.twse.com.tw) for director/supervisor equity. Form 4 coverage below covers the EDGAR-reported ADR/common share transactions for the last 12 months.

Recent Transactions (Most Recent First)

Buys - Reading the Signal

The ESPP transactions throughout this list are scheduled, plan-driven acquisitions under TSMC's employee stock purchase program. They are purchased at a discount to market price under predetermined plan terms. While they confirm ongoing employee participation, they are not discretionary signals of conviction.

The notable transaction is Ursula Burns' March 31, 2026 open-market purchase of 1,000 ADS for approximately $322,050. Burns serves as an independent board director. This is an open-market, discretionary purchase - not an ESPP transaction, not a vesting event. For a director of a company of this size to write a $322,000 check to add to her stock position in the open market is a meaningful signal of personal conviction. It tripled her direct ADS holdings from 2,000 to 3,000. Burns is a former CEO of Xerox and sits on the boards of major corporations - she understands how to read a business.

This purchase qualifies as a bullish signal - it is a material, open-market, discretionary buy by a senior independent director at a price that reflects deliberate investment conviction rather than routine compensation.

C.C. Wei's own holdings are substantial: 7,452,349 shares held directly, plus 700,261 through his spouse, plus ESPP and LTI plan trust holdings. His ESPP additions are small relative to his existing position but confirm continuous participation.

Net Assessment

Insider activity is net-positive. The ESPP purchases reflect routine participation that is universally present across the executive team - not a strong signal either way. Ursula Burns' open-market purchase stands out as a genuine conviction buy - a non-routine, discretionary addition to a position at a price that was high in absolute terms. There is no meaningful insider selling in the disclosed filings over the last 12 months.

The limited volume of discretionary open-market purchases by executives (as opposed to directors) is common at very large, very expensive companies - at $322/ADS, buying meaningful size requires multi-million dollar commitments. The Burns purchase is the clearest signal available, and it is bullish.

Section 12: Scenarios

Bull Case

The AI infrastructure supercycle runs longer and deeper than any comparable technology investment wave. Hyperscalers - Microsoft, Google, Amazon, Meta - commit multi-year capital to AI clusters because they have found genuine monetizable use cases in enterprise AI, search, autonomous agents, and scientific discovery. The shift to agentic AI drives persistent inference demand that is structurally higher than a query-response model. TSMC's N2 ramps successfully through 2026, with yields tracking ahead of N3's ramp curve. The Arizona fabs achieve parity with Taiwan yields by 2027 ahead of schedule, unlocking faster overseas capacity expansion without the margin penalty. N3 supply remains so tight that TSMC exercises pricing power - quietly raising wafer prices as customers compete for limited capacity. The A14 node arrives on its 2028 schedule with strong customer adoption from both AI accelerator designers and Apple, sustaining the premium node mix that drives gross margins into the high 60s percent. TSMC's geographic diversification (US, Japan, Germany) satisfies both government requirements and customer supply security demands without meaningful margin degradation as overseas cost structures improve with operational maturity. The dividend grows above 20% per year through the decade.

Base Case

TSMC executes on its stated roadmap with characteristic consistency. N2 ramps steadily through 2026, reaching significant revenue contribution by H2 and gradually eclipsing N3 as the primary leading-edge node by 2027-2028. Arizona Fab 2 enters production on its H2 2027 schedule, adding meaningful N3 capacity outside Taiwan. AI demand growth continues at a strong but not parabolic rate - a 25-30% annual revenue growth trajectory through 2026-2027, consistent with the management-guided five-year framework. Gross margins fluctuate in the 62-67% range depending on FX and overseas ramp timing but generally remain above the "56% and higher" through-cycle target. The 2027 arrival of A16 provides the next technology platform with BSPDN, and early HPC customer tape-outs validate demand before volume production. Dividends grow steadily in the 15-20% annual range. Geopolitics remain tense but not disruptive.

Bear Case

The AI investment cycle hits a digestion phase in 2027-2028. Hyperscalers, having built out massive GPU clusters, find that model quality gains are not translating to monetizable applications at the speed required to justify continued hardware spend. New orders slow materially. Simultaneously, TSMC is ramping Arizona Fab 2 and Taiwan Tainan N3 fabs, adding significant capacity just as demand growth moderates. The combination of high depreciation growth (committed CapEx does not slow), lower utilization, and overseas fab cost dilution compresses gross margins toward the 56% floor. N2 ramp proves slower than expected due to GAA yield challenges at high volume - a pattern seen in Samsung's 3nm rollout - pushing the N2 revenue contribution curve to the right. Apple, frustrated with Taiwan concentration risk and under pressure from the US government, qualifies Intel's 18A for base M-series chips and shifts 20-30% of its TSMC volume, reducing TSMC's smartphone platform revenue and signaling to other customers that alternatives are viable. Taiwan geopolitical tensions escalate enough to cause meaningful customer diversification away from Taiwan-sourced chips, accelerating the overseas cost dilution problem rather than mitigating it over time. Dividend growth slows to low single digits as capital is preserved for an extended investment cycle with lower returns.

Section 13: Further Reading

• Apple-TSMC: The Partnership That Built Modern Semiconductors - SemiAnalysis [paid]

• Clash of the Foundries: Gate All Around + Backside Power at 2nm - SemiAnalysis [paid]

• TSMC: The Most Mission-Critical Company on Earth - MBI Deep Dives [paid]

• TSMC 1Q'26 Update - MBI Deep Dives [paid]

• TSMC Risk - Stratechery [paid]

Sources:

• TSMC Q1 2026 Earnings Call - Investing.com
• TSMC Q4 2025 Earnings Call - Investing.com
• TSMC Q3 2025 Earnings Call - Motley Fool
• TSMC Q2 2025 Earnings Call - Investing.com
• TSMC 2026 Q1 Quarterly Results - Investor Relations
• TSMC 2025 Annual Report (20-F) - StockTitan
• TSMC Files Annual Report on Form 20-F for 2025 - BusinessWire
• TSMC Global Foundry Market Share ~70% - Design-Reuse
• TSMC vs Samsung Market Share Data - PatentPC
• TSMC Customer Rankings 2026 - CNBC Nvidia/Apple
• TSMC Arizona N3 Expansion - TrendForce
• TSMC Technology Roadmap A12/A13/A16 - Tom's Hardware
• TSMC Tech Symposium 2026 - SemiEngineering
• TSMC Founding History - Quartr
• Semiconductor Foundry Industry Growth - Precedence Research
• AI-Driven Foundry Revenue 2026 - TelecomLead/TrendForce
• SEMI Advanced Capacity Forecast - SEMI.org
• TSM Dividend History - StockAnalysis
• Ursula Burns ADS Purchase Form 4 - StockTitan
• C.C. Wei ESPP Purchase Form 4 - StockTitan
• SemiAnalysis TSMC Coverage Index
• MBI Deep Dives TSMC Coverage